The main restriction with this design is it results in one ISA target per board. The ISA is declared per core. To make the design simpler it's assumed a Processor (a collection of cores) are all of the same ISA. As each board has one processor, this also means a board is typically tied to one ISA per simulation. In order to remain backwards compatible and maintain the standard library APIs, this patch adds a `--main-isa` parameter which will determine what `gem5.runtime.get_runtime_isa` returns in cases where mutliple ISAs are compiled in. When setting the ISA in a simulation (via the Processor or Cores), the user may, as before, choose not to and, in this case, the `gem5.runtime.get_runtime_isa` function is used. The `gem5.runtime.get_runtime_isa` function is an intermediate step which should be removed in future versions of gem5 (users should specify precisely what ISA they want via configuration scripts). For this reason it throws a warning when used and should not be heavily relied upon. It is deprecated. Change-Id: Ia76541bfa9a5a4b6b86401309281849b49dc724b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55423 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
140 lines
5.3 KiB
Python
140 lines
5.3 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This script shows an example of running a full system Ubuntu boot simulation
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using the gem5 library. This simulation boots Ubuntu 18.04 using 2 KVM CPU
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cores. The simulation then switches to 2 Timing CPU cores before running an
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echo statement.
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Usage
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-----
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```
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scons build/X86/gem5.opt
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./build/X86/gem5.opt configs/example/gem5_library/x86-ubuntu-run-with-kvm.py
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```
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"""
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from gem5.utils.requires import requires
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from gem5.components.boards.x86_board import X86Board
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from gem5.components.memory.single_channel import SingleChannelDDR3_1600
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from gem5.components.processors.simple_switchable_processor import (
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SimpleSwitchableProcessor,
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)
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.isas import ISA
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from gem5.coherence_protocol import CoherenceProtocol
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from gem5.resources.resource import Resource
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from gem5.simulate.simulator import Simulator
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from gem5.simulate.exit_event import ExitEvent
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# This runs a check to ensure the gem5 binary is compiled to X86 and to the
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# MESI Two Level coherence protocol.
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requires(
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isa_required=ISA.X86,
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coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL,
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kvm_required=True,
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)
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from gem5.components.cachehierarchies.ruby.\
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mesi_two_level_cache_hierarchy import (
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MESITwoLevelCacheHierarchy,
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)
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# Here we setup a MESI Two Level Cache Hierarchy.
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cache_hierarchy = MESITwoLevelCacheHierarchy(
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l1d_size="16kB",
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l1d_assoc=8,
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l1i_size="16kB",
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l1i_assoc=8,
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l2_size="256kB",
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l2_assoc=16,
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num_l2_banks=1,
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)
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# Setup the system memory.
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memory = SingleChannelDDR3_1600(size="3GB")
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# Here we setup the processor. This is a special switchable processor in which
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# a starting core type and a switch core type must be specified. Once a
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# configuration is instantiated a user may call `processor.switch()` to switch
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# from the starting core types to the switch core types. In this simulation
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# we start with KVM cores to simulate the OS boot, then switch to the Timing
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# cores for the command we wish to run after boot.
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processor = SimpleSwitchableProcessor(
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starting_core_type=CPUTypes.KVM,
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switch_core_type=CPUTypes.TIMING,
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isa=ISA.X86,
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num_cores=2,
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)
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# Here we setup the board. The X86Board allows for Full-System X86 simulations.
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board = X86Board(
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clk_freq="3GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Here we set the Full System workload.
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# The `set_kernel_disk_workload` function for the X86Board takes a kernel, a
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# disk image, and, optionally, a command to run.
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# This is the command to run after the system has booted. The first `m5 exit`
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# will stop the simulation so we can switch the CPU cores from KVM to timing
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# and continue the simulation to run the echo command, sleep for a second,
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# then, again, call `m5 exit` to terminate the simulation. After simulation
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# has ended you may inspect `m5out/system.pc.com_1.device` to see the echo
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# output.
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command = "m5 exit;" \
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+ "echo 'This is running on Timing CPU cores.';" \
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+ "sleep 1;" \
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+ "m5 exit;"
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board.set_kernel_disk_workload(
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# The x86 linux kernel will be automatically downloaded to the if not
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# already present.
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kernel=Resource("x86-linux-kernel-5.4.49"),
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# The x86 ubuntu image will be automatically downloaded to the if not
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# already present.
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disk_image=Resource("x86-ubuntu-18.04-img"),
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readfile_contents=command,
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)
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simulator = Simulator(
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board=board,
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on_exit_event={
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# Here we want override the default behavior for the first m5 exit
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# exit event. Instead of exiting the simulator, we just want to
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# switch the processor. The 2nd m5 exit after will revert to using
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# default behavior where the simulator run will exit.
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ExitEvent.EXIT : (func() for func in [processor.switch]),
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},
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)
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simulator.run()
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