79a93f3429
The main restriction with this design is it results in one ISA target per board. The ISA is declared per core. To make the design simpler it's assumed a Processor (a collection of cores) are all of the same ISA. As each board has one processor, this also means a board is typically tied to one ISA per simulation. In order to remain backwards compatible and maintain the standard library APIs, this patch adds a `--main-isa` parameter which will determine what `gem5.runtime.get_runtime_isa` returns in cases where mutliple ISAs are compiled in. When setting the ISA in a simulation (via the Processor or Cores), the user may, as before, choose not to and, in this case, the `gem5.runtime.get_runtime_isa` function is used. The `gem5.runtime.get_runtime_isa` function is an intermediate step which should be removed in future versions of gem5 (users should specify precisely what ISA they want via configuration scripts). For this reason it throws a warning when used and should not be heavily relied upon. It is deprecated. Change-Id: Ia76541bfa9a5a4b6b86401309281849b49dc724b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/55423 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
93 lines
3.8 KiB
Python
93 lines
3.8 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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"""
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This example runs a simple linux boot. It uses the 'riscv-disk-img' resource.
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It is built with the sources in `src/riscv-fs` in [gem5 resources](
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https://gem5.googlesource.com/public/gem5-resources).
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Characteristics
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---------------
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* Runs exclusively on the RISC-V ISA with the classic caches
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* Assumes that the kernel is compiled into the bootloader
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* Automatically generates the DTB file
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* Will boot but requires a user to login using `m5term` (username: `root`,
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password: `root`)
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"""
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from gem5.components.boards.riscv_board import RiscvBoard
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from gem5.components.memory import SingleChannelDDR3_1600
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from gem5.components.processors.simple_processor import SimpleProcessor
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from gem5.components.cachehierarchies.classic.\
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private_l1_private_l2_cache_hierarchy import (
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PrivateL1PrivateL2CacheHierarchy,
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)
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from gem5.components.processors.cpu_types import CPUTypes
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from gem5.isas import ISA
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from gem5.utils.requires import requires
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from gem5.resources.resource import Resource
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from gem5.simulate.simulator import Simulator
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# Run a check to ensure the right version of gem5 is being used.
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requires(isa_required=ISA.RISCV)
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# Setup the cache hierarchy.
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# For classic, PrivateL1PrivateL2 and NoCache have been tested.
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# For Ruby, MESI_Two_Level and MI_example have been tested.
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cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
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l1d_size="32KiB", l1i_size="32KiB", l2_size="512KiB"
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)
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# Setup the system memory.
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memory = SingleChannelDDR3_1600()
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# Setup a single core Processor.
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processor = SimpleProcessor(
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cpu_type=CPUTypes.TIMING, isa=ISA.RISCV, num_cores=1
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)
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# Setup the board.
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board = RiscvBoard(
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clk_freq="1GHz",
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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)
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# Set the Full System workload.
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board.set_kernel_disk_workload(
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kernel=Resource("riscv-bootloader-vmlinux-5.10"),
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disk_image=Resource("riscv-disk-img"),
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)
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simulator = Simulator(board=board)
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print("Beginning simulation!")
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# Note: This simulation will never stop. You can access the terminal upon boot
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# using m5term (`./util/term`): `./m5term localhost <port>`. Note the `<port>`
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# value is obtained from the gem5 terminal stdout. Look out for
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# "system.platform.terminal: Listening for connections on port <port>".
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simulator.run() |