Andreas Hansson 7a61f667f0 cpu: Fix timing CPU drain check ...

This patch modifies the SimpleTimingCPU drain check to also consider
the fetch event. Previously, there was an assumption that there is
never a fetch event scheduled if the CPU is not executing
microcode. However, when a context is activated, a fetch even is
scheduled, and microPC() is zero.

2013-08-19 03:52:30 -04:00

..

atomic.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

atomic.hh

cpu: Make hash struct instead of class to please clang

2013-05-30 12:53:52 -04:00

AtomicSimpleCPU.py

cpu: generate SimPoint basic block vector profiles

2013-04-22 13:20:31 -04:00

base.cc

base simple cpu: removes commented out code about cache ops

2013-01-12 22:11:16 -06:00

base.hh

x86: Changes to decoder, corrects 9376

2013-01-12 22:09:48 -06:00

BaseSimpleCPU.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

timing.cc

cpu: Fix timing CPU drain check

2013-08-19 03:52:30 -04:00

timing.hh

cpu: Fix timing CPU drain check

2013-08-19 03:52:30 -04:00

TimingSimpleCPU.py

cpu: Add CPU metadata om the Python classes

2013-02-15 17:40:08 -05:00