7a0d5aafe4
This patch is the final patch in a series of patches. The aim of the series is to make ruby more configurable than it was. More specifically, the connections between controllers are not at all possible (unless one is ready to make significant changes to the coherence protocol). Moreover the buffers themselves are magically connected to the network inside the slicc code. These connections are not part of the configuration file. This patch makes changes so that these connections will now be made in the python configuration files associated with the protocols. This requires each state machine to expose the message buffers it uses for input and output. So, the patch makes these buffers configurable members of the machines. The patch drops the slicc code that usd to connect these buffers to the network. Now these buffers are exposed to the python configuration system as Master and Slave ports. In the configuration files, any master port can be connected any slave port. The file pyobject.cc has been modified to take care of allocating the actual message buffer. This is inline with how other port connections work.
664 lines
21 KiB
Plaintext
664 lines
21 KiB
Plaintext
/*
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* Copyright (c) 2009-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2010-2012 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(Directory, "Directory protocol")
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: DirectoryMemory * directory;
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MemoryControl * memBuffer;
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Cycles directory_latency := 12;
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MessageBuffer * forwardFromDir, network="To", virtual_network="3",
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ordered="false", vnet_type="forward";
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MessageBuffer * responseFromDir, network="To", virtual_network="4",
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ordered="false", vnet_type="response";
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MessageBuffer * dmaResponseFromDir, network="To", virtual_network="1",
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ordered="true", vnet_type="response";
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MessageBuffer * requestToDir, network="From", virtual_network="2",
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ordered="true", vnet_type="request";
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MessageBuffer * dmaRequestToDir, network="From", virtual_network="0",
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ordered="true", vnet_type="request";
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{
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// STATES
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state_declaration(State, desc="Directory states", default="Directory_State_I") {
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// Base states
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I, AccessPermission:Read_Write, desc="Invalid";
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M, AccessPermission:Invalid, desc="Modified";
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M_DRD, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA read";
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M_DWR, AccessPermission:Busy, desc="Blocked on an invalidation for a DMA write";
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M_DWRI, AccessPermission:Busy, desc="Intermediate state M_DWR-->I";
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M_DRDI, AccessPermission:Busy, desc="Intermediate state M_DRD-->I";
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IM, AccessPermission:Busy, desc="Intermediate state I-->M";
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MI, AccessPermission:Busy, desc="Intermediate state M-->I";
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ID, AccessPermission:Busy, desc="Intermediate state for DMA_READ when in I";
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ID_W, AccessPermission:Busy, desc="Intermediate state for DMA_WRITE when in I";
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}
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// Events
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enumeration(Event, desc="Directory events") {
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// processor requests
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GETX, desc="A GETX arrives";
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GETS, desc="A GETS arrives";
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PUTX, desc="A PUTX arrives";
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PUTX_NotOwner, desc="A PUTX arrives";
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// DMA requests
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DMA_READ, desc="A DMA Read memory request";
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DMA_WRITE, desc="A DMA Write memory request";
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// Memory Controller
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Memory_Data, desc="Fetched data from memory arrives";
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Memory_Ack, desc="Writeback Ack from memory arrives";
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}
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// TYPES
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// DirectoryEntry
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structure(Entry, desc="...", interface="AbstractEntry") {
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State DirectoryState, desc="Directory state";
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DataBlock DataBlk, desc="data for the block";
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NetDest Sharers, desc="Sharers for this block";
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NetDest Owner, desc="Owner of this block";
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}
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// TBE entries for DMA requests
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structure(TBE, desc="TBE entries for outstanding DMA requests") {
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Address PhysicalAddress, desc="physical address";
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State TBEState, desc="Transient State";
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DataBlock DataBlk, desc="Data to be written (DMA write only)";
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int Len, desc="...";
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MachineID DmaRequestor, desc="DMA requestor";
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}
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structure(TBETable, external="yes") {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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// ** OBJECTS **
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TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
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void set_tbe(TBE b);
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void unset_tbe();
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Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
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Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);
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if (is_valid(dir_entry)) {
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return dir_entry;
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}
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dir_entry := static_cast(Entry, "pointer",
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directory.allocate(addr, new Entry));
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return dir_entry;
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}
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State getState(TBE tbe, Address addr) {
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if (is_valid(tbe)) {
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return tbe.TBEState;
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} else if (directory.isPresent(addr)) {
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return getDirectoryEntry(addr).DirectoryState;
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} else {
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return State:I;
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}
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}
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void setState(TBE tbe, Address addr, State state) {
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if (is_valid(tbe)) {
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tbe.TBEState := state;
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}
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if (directory.isPresent(addr)) {
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if (state == State:M) {
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assert(getDirectoryEntry(addr).Owner.count() == 1);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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}
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getDirectoryEntry(addr).DirectoryState := state;
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if (state == State:I) {
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assert(getDirectoryEntry(addr).Owner.count() == 0);
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assert(getDirectoryEntry(addr).Sharers.count() == 0);
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directory.invalidateBlock(addr);
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}
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}
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}
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AccessPermission getAccessPermission(Address addr) {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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return Directory_State_to_permission(tbe.TBEState);
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}
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if(directory.isPresent(addr)) {
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return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
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}
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return AccessPermission:NotPresent;
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}
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void setAccessPermission(Address addr, State state) {
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if (directory.isPresent(addr)) {
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getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
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}
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}
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DataBlock getDataBlock(Address addr), return_by_ref="yes" {
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TBE tbe := TBEs[addr];
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if(is_valid(tbe)) {
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return tbe.DataBlk;
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}
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return getDirectoryEntry(addr).DataBlk;
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}
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// ** OUT_PORTS **
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out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
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out_port(responseNetwork_out, ResponseMsg, responseFromDir);
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out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests
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out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaResponseFromDir);
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//added by SS
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out_port(memQueue_out, MemoryMsg, memBuffer);
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// ** IN_PORTS **
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in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) {
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if (dmaRequestQueue_in.isReady()) {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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TBE tbe := TBEs[in_msg.LineAddress];
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if (in_msg.Type == DMARequestType:READ) {
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trigger(Event:DMA_READ, in_msg.LineAddress, tbe);
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} else if (in_msg.Type == DMARequestType:WRITE) {
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trigger(Event:DMA_WRITE, in_msg.LineAddress, tbe);
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} else {
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error("Invalid message");
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}
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}
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}
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}
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in_port(requestQueue_in, RequestMsg, requestToDir) {
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if (requestQueue_in.isReady()) {
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peek(requestQueue_in, RequestMsg) {
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TBE tbe := TBEs[in_msg.Addr];
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if (in_msg.Type == CoherenceRequestType:GETS) {
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trigger(Event:GETS, in_msg.Addr, tbe);
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} else if (in_msg.Type == CoherenceRequestType:GETX) {
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trigger(Event:GETX, in_msg.Addr, tbe);
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} else if (in_msg.Type == CoherenceRequestType:PUTX) {
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if (getDirectoryEntry(in_msg.Addr).Owner.isElement(in_msg.Requestor)) {
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trigger(Event:PUTX, in_msg.Addr, tbe);
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} else {
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trigger(Event:PUTX_NotOwner, in_msg.Addr, tbe);
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}
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} else {
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error("Invalid message");
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}
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}
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}
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}
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//added by SS
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// off-chip memory request/response is done
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in_port(memQueue_in, MemoryMsg, memBuffer) {
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if (memQueue_in.isReady()) {
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peek(memQueue_in, MemoryMsg) {
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TBE tbe := TBEs[in_msg.Addr];
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if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
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trigger(Event:Memory_Data, in_msg.Addr, tbe);
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} else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
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trigger(Event:Memory_Ack, in_msg.Addr, tbe);
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} else {
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DPRINTF(RubySlicc,"%s\n", in_msg.Type);
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error("Invalid message");
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}
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}
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}
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}
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// Actions
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action(a_sendWriteBackAck, "a", desc="Send writeback ack to requestor") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceRequestType:WB_ACK;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(l_sendWriteBackAck, "la", desc="Send writeback ack to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(forwardNetwork_out, RequestMsg, 1) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceRequestType:WB_ACK;
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out_msg.Requestor := in_msg.OriginalRequestorMachId;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(b_sendWriteBackNack, "b", desc="Send writeback nack to requestor") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceRequestType:WB_NACK;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(c_clearOwner, "c", desc="Clear the owner field") {
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getDirectoryEntry(address).Owner.clear();
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}
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action(d_sendData, "d", desc="Send data to requestor") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(responseNetwork_out, ResponseMsg, 1) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.OriginalRequestorMachId);
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out_msg.DataBlk := in_msg.DataBlk;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
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peek(memQueue_in, MemoryMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) {
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assert(is_valid(tbe));
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(tbe.DmaRequestor);
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) {
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assert(is_valid(tbe));
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:DATA;
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out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
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out_msg.Destination.add(tbe.DmaRequestor);
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
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enqueue(dmaResponseNetwork_out, DMAResponseMsg, 1) {
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assert(is_valid(tbe));
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out_msg.PhysicalAddress := address;
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out_msg.LineAddress := address;
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out_msg.Type := DMAResponseType:ACK;
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out_msg.Destination.add(tbe.DmaRequestor);
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(e_ownerIsRequestor, "e", desc="The owner is now the requestor") {
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peek(requestQueue_in, RequestMsg) {
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getDirectoryEntry(address).Owner.clear();
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getDirectoryEntry(address).Owner.add(in_msg.Requestor);
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}
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}
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action(f_forwardRequest, "f", desc="Forward request to owner") {
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peek(requestQueue_in, RequestMsg) {
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APPEND_TRANSITION_COMMENT("Own: ");
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APPEND_TRANSITION_COMMENT(getDirectoryEntry(in_msg.Addr).Owner);
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APPEND_TRANSITION_COMMENT("Req: ");
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APPEND_TRANSITION_COMMENT(in_msg.Requestor);
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enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
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out_msg.Addr := address;
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out_msg.Type := in_msg.Type;
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out_msg.Requestor := in_msg.Requestor;
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out_msg.Destination := getDirectoryEntry(in_msg.Addr).Owner;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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enqueue(forwardNetwork_out, RequestMsg, directory_latency) {
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out_msg.Addr := address;
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out_msg.Type := CoherenceRequestType:INV;
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out_msg.Requestor := machineID;
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out_msg.Destination := getDirectoryEntry(in_msg.PhysicalAddress).Owner;
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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}
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action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") {
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requestQueue_in.dequeue();
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}
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action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") {
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dmaRequestQueue_in.dequeue();
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}
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action(l_writeDataToMemory, "pl", desc="Write PUTX data to memory") {
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peek(requestQueue_in, RequestMsg) {
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// assert(in_msg.Dirty);
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// assert(in_msg.MessageSize == MessageSizeType:Writeback_Data);
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getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
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//getDirectoryEntry(in_msg.Addr).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len);
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}
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}
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action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
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assert(is_valid(tbe));
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getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
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}
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action(v_allocateTBE, "v", desc="Allocate TBE") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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tbe.DataBlk := in_msg.DataBlk;
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tbe.PhysicalAddress := in_msg.PhysicalAddress;
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tbe.Len := in_msg.Len;
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tbe.DmaRequestor := in_msg.Requestor;
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}
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}
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action(r_allocateTbeForDmaRead, "\r", desc="Allocate TBE for DMA Read") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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tbe.DmaRequestor := in_msg.Requestor;
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}
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}
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action(v_allocateTBEFromRequestNet, "\v", desc="Allocate TBE") {
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peek(requestQueue_in, RequestMsg) {
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TBEs.allocate(address);
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set_tbe(TBEs[address]);
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tbe.DataBlk := in_msg.DataBlk;
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}
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}
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action(w_deallocateTBE, "w", desc="Deallocate TBE") {
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TBEs.deallocate(address);
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unset_tbe();
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}
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action(z_recycleRequestQueue, "z", desc="recycle request queue") {
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requestQueue_in.recycle();
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}
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action(y_recycleDMARequestQueue, "y", desc="recycle dma request queue") {
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dmaRequestQueue_in.recycle();
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}
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action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") {
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peek(requestQueue_in, RequestMsg) {
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enqueue(memQueue_out, MemoryMsg, 1) {
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out_msg.Addr := address;
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out_msg.Type := MemoryRequestType:MEMORY_READ;
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out_msg.Sender := machineID;
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out_msg.OriginalRequestorMachId := in_msg.Requestor;
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out_msg.MessageSize := in_msg.MessageSize;
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out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
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DPRINTF(RubySlicc,"%s\n", out_msg);
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}
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}
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}
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action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") {
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peek(dmaRequestQueue_in, DMARequestMsg) {
|
|
enqueue(memQueue_out, MemoryMsg, 1) {
|
|
out_msg.Addr := address;
|
|
out_msg.Type := MemoryRequestType:MEMORY_READ;
|
|
out_msg.Sender := machineID;
|
|
//out_msg.OriginalRequestorMachId := machineID;
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
|
|
DPRINTF(RubySlicc,"%s\n", out_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") {
|
|
peek(dmaRequestQueue_in, DMARequestMsg) {
|
|
enqueue(memQueue_out, MemoryMsg, 1) {
|
|
out_msg.Addr := address;
|
|
out_msg.Type := MemoryRequestType:MEMORY_WB;
|
|
//out_msg.OriginalRequestorMachId := machineID;
|
|
//out_msg.DataBlk := in_msg.DataBlk;
|
|
out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len);
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
//out_msg.Prefetch := in_msg.Prefetch;
|
|
|
|
DPRINTF(RubySlicc,"%s\n", out_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip writeback request") {
|
|
peek(requestQueue_in, RequestMsg) {
|
|
enqueue(memQueue_out, MemoryMsg, 1) {
|
|
assert(is_valid(tbe));
|
|
out_msg.Addr := address;
|
|
out_msg.Type := MemoryRequestType:MEMORY_WB;
|
|
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
|
// get incoming data
|
|
// out_msg.DataBlk := in_msg.DataBlk;
|
|
out_msg.DataBlk.copyPartial(tbe.DataBlk, addressOffset(tbe.PhysicalAddress), tbe.Len);
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
//out_msg.Prefetch := in_msg.Prefetch;
|
|
|
|
DPRINTF(RubySlicc,"%s\n", out_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
action(l_queueMemoryWBRequest, "lq", desc="Write PUTX data to memory") {
|
|
peek(requestQueue_in, RequestMsg) {
|
|
enqueue(memQueue_out, MemoryMsg, 1) {
|
|
out_msg.Addr := address;
|
|
out_msg.Type := MemoryRequestType:MEMORY_WB;
|
|
out_msg.Sender := machineID;
|
|
out_msg.OriginalRequestorMachId := in_msg.Requestor;
|
|
out_msg.DataBlk := in_msg.DataBlk;
|
|
out_msg.MessageSize := in_msg.MessageSize;
|
|
|
|
DPRINTF(RubySlicc,"%s\n", out_msg);
|
|
}
|
|
}
|
|
}
|
|
|
|
action(l_popMemQueue, "q", desc="Pop off-chip request queue") {
|
|
memQueue_in.dequeue();
|
|
}
|
|
|
|
action(w_writeDataToMemoryFromTBE, "\w", desc="Write date to directory memory from TBE") {
|
|
assert(is_valid(tbe));
|
|
getDirectoryEntry(address).DataBlk := TBEs[address].DataBlk;
|
|
}
|
|
|
|
// TRANSITIONS
|
|
|
|
transition({M_DRD, M_DWR, M_DWRI, M_DRDI}, GETX) {
|
|
z_recycleRequestQueue;
|
|
}
|
|
|
|
transition({IM, MI, ID, ID_W}, {GETX, GETS, PUTX, PUTX_NotOwner} ) {
|
|
z_recycleRequestQueue;
|
|
}
|
|
|
|
transition({IM, MI, ID, ID_W}, {DMA_READ, DMA_WRITE} ) {
|
|
y_recycleDMARequestQueue;
|
|
}
|
|
|
|
|
|
transition(I, GETX, IM) {
|
|
//d_sendData;
|
|
qf_queueMemoryFetchRequest;
|
|
e_ownerIsRequestor;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(IM, Memory_Data, M) {
|
|
d_sendData;
|
|
//e_ownerIsRequestor;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
|
|
transition(I, DMA_READ, ID) {
|
|
//dr_sendDMAData;
|
|
r_allocateTbeForDmaRead;
|
|
qf_queueMemoryFetchRequestDMA;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(ID, Memory_Data, I) {
|
|
dr_sendDMAData;
|
|
//p_popIncomingDMARequestQueue;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
|
|
|
|
transition(I, DMA_WRITE, ID_W) {
|
|
v_allocateTBE;
|
|
qw_queueMemoryWBRequest_partial;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(ID_W, Memory_Ack, I) {
|
|
dwt_writeDMADataFromTBE;
|
|
da_sendDMAAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, DMA_READ, M_DRD) {
|
|
v_allocateTBE;
|
|
inv_sendCacheInvalidate;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(M_DRD, PUTX, M_DRDI) {
|
|
l_writeDataToMemory;
|
|
drp_sendDMAData;
|
|
c_clearOwner;
|
|
l_queueMemoryWBRequest;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DRDI, Memory_Ack, I) {
|
|
l_sendWriteBackAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
|
|
transition(M, DMA_WRITE, M_DWR) {
|
|
v_allocateTBE;
|
|
inv_sendCacheInvalidate;
|
|
p_popIncomingDMARequestQueue;
|
|
}
|
|
|
|
transition(M_DWR, PUTX, M_DWRI) {
|
|
l_writeDataToMemory;
|
|
qw_queueMemoryWBRequest_partialTBE;
|
|
c_clearOwner;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M_DWRI, Memory_Ack, I) {
|
|
w_writeDataToMemoryFromTBE;
|
|
l_sendWriteBackAck;
|
|
da_sendDMAAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, GETX, M) {
|
|
f_forwardRequest;
|
|
e_ownerIsRequestor;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(M, PUTX, MI) {
|
|
c_clearOwner;
|
|
v_allocateTBEFromRequestNet;
|
|
l_queueMemoryWBRequest;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(MI, Memory_Ack, I) {
|
|
w_writeDataToMemoryFromTBE;
|
|
l_sendWriteBackAck;
|
|
w_deallocateTBE;
|
|
l_popMemQueue;
|
|
}
|
|
|
|
transition(M, PUTX_NotOwner, M) {
|
|
b_sendWriteBackNack;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
transition(I, PUTX_NotOwner, I) {
|
|
b_sendWriteBackNack;
|
|
i_popIncomingRequestQueue;
|
|
}
|
|
|
|
}
|