0b54ad277f
The purpose of the gem5 components library is to provide gem5 users a standard set of common and useful gem5 components pre-built to add to their experiments. The gem5 components library adopts a modular architecture design with the goal of components being easy to add and remove from designs, and extendable as needed. E.g., any Memory system should be interchangable with any other, and if not a helpful error messages should be raised. Examples of using the gem5 components library can be found in `configs/example/components-library`. Important Disclaimer: This is a pre-alpha release of the gem5 components library. The purpose of this release is to get some community feedback on this new component of gem5. Though some testing has been done, we expect regular fixes and improvements until this is in a stable state. The components library has been formatted with Python Black; typing has been checked with MyPy; and the library has been tested with the scripts in `configs/example/components-libary`. More rigorous tests are to be added in future revisions. More detailed documentation will appear in future revisions. Jira Ticket outlining TODOs and known bugs can be found here: https://gem5.atlassian.net/browse/GEM5-648 Change-Id: I3492ec4a6d8c59ffbae899ce8e87ab4ffb92b976 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47466 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
77 lines
3.2 KiB
Python
77 lines
3.2 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All Rights Reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from abc import abstractmethod
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from components_library.isas import ISA
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from components_library.processors.cpu_types import CPUTypes
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from components_library.processors.abstract_core import AbstractCore
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from m5.objects import L1Cache_Controller
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import math
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class AbstractL1Cache(L1Cache_Controller):
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_version = 0
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@classmethod
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def versionCount(cls):
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cls._version += 1 # Use count for this particular type
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return cls._version - 1
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# TODO: I don't love that we have to pass in the cache line size.
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# However, we need some way to set the index bits
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def __init__(self, network, cache_line_size):
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""" """
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super(AbstractL1Cache, self).__init__()
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self.version = self.versionCount()
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self._cache_line_size = cache_line_size
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self.connectQueues(network)
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def getBlockSizeBits(self):
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bits = int(math.log(self._cache_line_size, 2))
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if 2 ** bits != self._cache_line_size.value:
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raise Exception("Cache line size not a power of 2!")
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return bits
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def sendEvicts(self, core: AbstractCore, target_isa: ISA):
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"""True if the CPU model or ISA requires sending evictions from caches
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to the CPU. Two scenarios warrant forwarding evictions to the CPU:
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1. The O3 model must keep the LSQ coherent with the caches
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2. The x86 mwait instruction is built on top of coherence
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3. The local exclusive monitor in ARM systems
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"""
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if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86, ISA.ARM):
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return True
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return False
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@abstractmethod
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def connectQueues(self, network):
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"""Connect all of the queues for this controller."""
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raise NotImplementedError
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