0b54ad277f
The purpose of the gem5 components library is to provide gem5 users a standard set of common and useful gem5 components pre-built to add to their experiments. The gem5 components library adopts a modular architecture design with the goal of components being easy to add and remove from designs, and extendable as needed. E.g., any Memory system should be interchangable with any other, and if not a helpful error messages should be raised. Examples of using the gem5 components library can be found in `configs/example/components-library`. Important Disclaimer: This is a pre-alpha release of the gem5 components library. The purpose of this release is to get some community feedback on this new component of gem5. Though some testing has been done, we expect regular fixes and improvements until this is in a stable state. The components library has been formatted with Python Black; typing has been checked with MyPy; and the library has been tested with the scripts in `configs/example/components-libary`. More rigorous tests are to be added in future revisions. More detailed documentation will appear in future revisions. Jira Ticket outlining TODOs and known bugs can be found here: https://gem5.atlassian.net/browse/GEM5-648 Change-Id: I3492ec4a6d8c59ffbae899ce8e87ab4ffb92b976 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47466 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
343 lines
11 KiB
Python
343 lines
11 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from components_library.utils.override import overrides
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from components_library.boards.abstract_board import AbstractBoard
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from components_library.isas import ISA
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import m5
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from m5.objects import (
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Cache,
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Pc,
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AddrRange,
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X86FsLinux,
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Addr,
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X86SMBiosBiosInformation,
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X86IntelMPProcessor,
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X86IntelMPIOAPIC,
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X86IntelMPBus,
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X86IntelMPBusHierarchy,
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X86IntelMPIOIntAssignment,
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X86E820Entry,
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Bridge,
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IOXBar,
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IdeDisk,
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CowDiskImage,
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RawDiskImage,
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BaseXBar,
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)
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from m5.params import Port
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from .simple_board import SimpleBoard
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from ..processors.abstract_processor import AbstractProcessor
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from ..memory.abstract_memory_system import AbstractMemorySystem
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from ..cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
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from ..runtime import get_runtime_isa
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import os
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from typing import Optional, Sequence
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class X86Board(SimpleBoard):
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"""
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A board capable of full system simulation for X86.
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**Limitations**
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* Currently, this board's memory is hardcoded to 3GB
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* Much of the I/O subsystem is hard coded
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"""
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def __init__(
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self,
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clk_freq: str,
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processor: AbstractProcessor,
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memory: AbstractMemorySystem,
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cache_hierarchy: AbstractCacheHierarchy,
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exit_on_work_items: bool = False,
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) -> None:
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super(X86Board, self).__init__(
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clk_freq=clk_freq,
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processor=processor,
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memory=memory,
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cache_hierarchy=cache_hierarchy,
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exit_on_work_items=exit_on_work_items,
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)
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if get_runtime_isa() != ISA.X86:
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raise EnvironmentError(
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"X86Motherboard will only work with the X86 ISA."
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)
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# Add the address range for the IO
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# TODO: This should definitely NOT be hardcoded to 3GB
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self.mem_ranges = [
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AddrRange(Addr("3GB")), # All data
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AddrRange(0xC0000000, size=0x100000), # For I/0
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]
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self.pc = Pc()
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self.workload = X86FsLinux()
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# Constants similar to x86_traits.hh
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IO_address_space_base = 0x8000000000000000
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pci_config_address_space_base = 0xC000000000000000
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interrupts_address_space_base = 0xA000000000000000
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APIC_range_size = 1 << 12
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# North Bridge
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self.iobus = IOXBar()
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# Setup memory system specific settings.
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if self.get_cache_hierarchy().is_ruby():
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self.pc.attachIO(self.get_io_bus(), [self.pc.south_bridge.ide.dma])
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else:
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self.bridge = Bridge(delay="50ns")
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self.bridge.mem_side_port = self.get_io_bus().cpu_side_ports
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self.bridge.cpu_side_port = (
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self.get_cache_hierarchy().get_mem_side_port()
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)
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# # Constants similar to x86_traits.hh
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IO_address_space_base = 0x8000000000000000
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pci_config_address_space_base = 0xC000000000000000
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interrupts_address_space_base = 0xA000000000000000
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APIC_range_size = 1 << 12
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self.bridge.ranges = [
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AddrRange(0xC0000000, 0xFFFF0000),
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AddrRange(
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IO_address_space_base, interrupts_address_space_base - 1
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),
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AddrRange(pci_config_address_space_base, Addr.max),
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]
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self.apicbridge = Bridge(delay="50ns")
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self.apicbridge.cpu_side_port = self.get_io_bus().mem_side_ports
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self.apicbridge.mem_side_port = (
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self.get_cache_hierarchy().get_cpu_side_port()
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)
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self.apicbridge.ranges = [
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AddrRange(
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interrupts_address_space_base,
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interrupts_address_space_base
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+ self.get_processor().get_num_cores() * APIC_range_size
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- 1,
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)
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]
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self.pc.attachIO(self.get_io_bus())
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self.iocache = Cache(
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assoc=8,
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tag_latency=50,
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data_latency=50,
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response_latency=50,
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mshrs=20,
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size="1kB",
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tgts_per_mshr=12,
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addr_ranges=self.mem_ranges,
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)
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self.iocache.cpu_side = self.get_io_bus().mem_side_ports
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self.iocache.mem_side = (
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self.get_cache_hierarchy().get_cpu_side_port()
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)
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# Add in a Bios information structure.
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self.workload.smbios_table.structures = [X86SMBiosBiosInformation()]
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# Set up the Intel MP table
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base_entries = []
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ext_entries = []
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for i in range(self.get_processor().get_num_cores()):
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bp = X86IntelMPProcessor(
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local_apic_id=i,
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local_apic_version=0x14,
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enable=True,
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bootstrap=(i == 0),
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)
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base_entries.append(bp)
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io_apic = X86IntelMPIOAPIC(
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id=self.get_processor().get_num_cores(),
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version=0x11,
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enable=True,
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address=0xFEC00000,
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)
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self.pc.south_bridge.io_apic.apic_id = io_apic.id
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base_entries.append(io_apic)
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pci_bus = X86IntelMPBus(bus_id=0, bus_type="PCI ")
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base_entries.append(pci_bus)
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isa_bus = X86IntelMPBus(bus_id=1, bus_type="ISA ")
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base_entries.append(isa_bus)
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connect_busses = X86IntelMPBusHierarchy(
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bus_id=1, subtractive_decode=True, parent_bus=0
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)
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ext_entries.append(connect_busses)
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pci_dev4_inta = X86IntelMPIOIntAssignment(
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interrupt_type="INT",
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polarity="ConformPolarity",
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trigger="ConformTrigger",
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source_bus_id=0,
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source_bus_irq=0 + (4 << 2),
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dest_io_apic_id=io_apic.id,
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dest_io_apic_intin=16,
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)
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base_entries.append(pci_dev4_inta)
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def assignISAInt(irq, apicPin):
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assign_8259_to_apic = X86IntelMPIOIntAssignment(
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interrupt_type="ExtInt",
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polarity="ConformPolarity",
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trigger="ConformTrigger",
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source_bus_id=1,
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source_bus_irq=irq,
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dest_io_apic_id=io_apic.id,
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dest_io_apic_intin=0,
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)
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base_entries.append(assign_8259_to_apic)
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assign_to_apic = X86IntelMPIOIntAssignment(
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interrupt_type="INT",
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polarity="ConformPolarity",
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trigger="ConformTrigger",
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source_bus_id=1,
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source_bus_irq=irq,
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dest_io_apic_id=io_apic.id,
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dest_io_apic_intin=apicPin,
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)
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base_entries.append(assign_to_apic)
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assignISAInt(0, 2)
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assignISAInt(1, 1)
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for i in range(3, 15):
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assignISAInt(i, i)
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self.workload.intel_mp_table.base_entries = base_entries
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self.workload.intel_mp_table.ext_entries = ext_entries
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entries = [
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# Mark the first megabyte of memory as reserved
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X86E820Entry(addr=0, size="639kB", range_type=1),
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X86E820Entry(addr=0x9FC00, size="385kB", range_type=2),
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# Mark the rest of physical memory as available
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X86E820Entry(
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addr=0x100000,
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size=f"{self.mem_ranges[0].size() - 0x100000:d}B",
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range_type=1,
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),
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]
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# Reserve the last 16kB of the 32-bit address space for m5ops
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entries.append(
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X86E820Entry(addr=0xFFFF0000, size="64kB", range_type=2)
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)
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self.workload.e820_table.entries = entries
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def connect_things(self) -> None:
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super().connect_things()
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def set_workload(
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self, kernel: str, disk_image: str, command: Optional[str] = None
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):
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"""Setup the full system files
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See <url> for the currently tested kernels and OSes.
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The command is an optional string to execute once the OS is fully
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booted, assuming the disk image is setup to run `m5 readfile` after
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booting.
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**Limitations**
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* Only supports a Linux kernel
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* Disk must be configured correctly to use the command option
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:param kernel: The compiled kernel binary
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:param disk_image: A disk image containing the OS data. The first
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partition should be the root partition.
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:param command: The command(s) to run with bash once the OS is booted
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"""
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# Set the Linux kernel to use.
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self.workload.object_file = kernel
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# Options specified on the kernel command line.
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self.workload.command_line = " ".join(
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[
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"earlyprintk=ttyS0",
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"console=ttyS0",
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"lpj=7999923",
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"root=/dev/hda1",
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]
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)
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# Create the Disk image SimObject.
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ide_disk = IdeDisk()
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ide_disk.driveID = "device0"
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ide_disk.image = CowDiskImage(
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child=RawDiskImage(read_only=True), read_only=False
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)
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ide_disk.image.child.image_file = disk_image
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# Attach the SimObject to the system.
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self.pc.south_bridge.ide.disks = [ide_disk]
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# Set the script to be passed to the simulated system to execute after
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# boot.
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if command:
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file_name = os.path.join(m5.options.outdir, "run")
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bench_file = open(file_name, "w+")
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bench_file.write(command)
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bench_file.close()
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# Set to the system readfile
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self.readfile = file_name
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@overrides(AbstractBoard)
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def has_io_bus(self) -> bool:
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return True
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@overrides(AbstractBoard)
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def get_io_bus(self) -> BaseXBar:
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return self.iobus
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@overrides(AbstractBoard)
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def has_dma_ports(self) -> bool:
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return True
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@overrides(AbstractBoard)
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def get_dma_ports(self) -> Sequence[Port]:
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return [self.pc.south_bridge.ide.dma, self.iobus.mem_side_ports]
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