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79b288f7b5c81f37d1b33470a1144d52efafb496
gem5/src/arch
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Gabe Black 79b288f7b5 ARM: Force the condition code for 16 bit thumb instructions to be unconditional.
Before, because 16 bit thumb instructions didn't set the upper 16 bits of the
ExtMachInst, that field would be interpretted as "equals".
2010-06-02 12:58:01 -05:00
..
alpha
tick: rename Clock namespace to SimClock
2010-04-15 16:24:12 -07:00
arm
ARM: Force the condition code for 16 bit thumb instructions to be unconditional.
2010-06-02 12:58:01 -05:00
mips
tick: rename Clock namespace to SimClock
2010-04-15 16:24:12 -07:00
power
cpu: fix exec tracing memory corruption bug
2010-03-23 08:50:57 -07:00
sparc
SPARC: Implement the version of movcc that uses the fp condition codes.
2010-05-14 14:22:51 -07:00
x86
x86: put back code that I accidentally deleted
2010-05-25 20:15:44 -07:00
isa_parser.py
ARM: Fix custom writer/reader code for non indexed operands.
2010-06-02 12:57:59 -05:00
micro_asm_test.py
Add a second section to make sure the ROM is extended properly.
2007-05-31 22:21:21 +00:00
micro_asm.py
scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access
2009-09-22 15:24:16 -07:00
SConscript
scons: import ply to work around scons sys.path weirdness
2010-03-10 15:39:34 -08:00
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