6fa49382ef
ARMv8 differs from ARMv7 with the presence of RVBAR register, which contains the implementation defined reset address when EL3 is not implemented. The entry 0x0 in the AArch32 vector table, once used for the Reset Vector, is now marked as "Not used", stating that it is now IMPLEMENTATION DEFINED. An implementation might still use this vector table entry to hold the Reset vector, but having a Reset address != than the general vector table (for any other exception) is allowed. At the moment any Reset exception is still using 0 as a vector table base address. This patch is extending the ArmSystem::resetAddr64 to ArmSystem::resetAddr so that it can be used for initializing MVBAR/RVBAR. In order to do so, we are providing a specialized behavior for the Reset exception when evaluating the vector base address. Change-Id: I051a730dc089e194db3b107bbed19251c661f87e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14000 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
157 lines
6.7 KiB
Python
157 lines
6.7 KiB
Python
# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Glenn Bergmans
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from m5.params import *
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from m5.SimObject import *
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from m5.util.fdthelper import *
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from System import System
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from ArmSemihosting import ArmSemihosting
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class ArmMachineType(Enum):
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map = {
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'RealViewPBX' : 1901,
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'VExpress_EMM' : 2272,
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'VExpress_EMM64' : 2272,
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'DTOnly' : -1,
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}
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class ArmSystem(System):
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type = 'ArmSystem'
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cxx_header = "arch/arm/system.hh"
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multi_proc = Param.Bool(True, "Multiprocessor system?")
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boot_loader = VectorParam.String([],
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"File that contains the boot loader code. Zero or more files may be "
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"specified. The first boot loader that matches the kernel's "
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"architecture will be used.")
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gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
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flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
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have_security = Param.Bool(False,
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"True if Security Extensions are implemented")
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have_virtualization = Param.Bool(False,
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"True if Virtualization Extensions are implemented")
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have_crypto = Param.Bool(False,
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"True if Crypto Extensions is implemented")
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have_lpae = Param.Bool(True, "True if LPAE is implemented")
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reset_addr = Param.Addr(0x0,
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"Reset address (ARMv8)")
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auto_reset_addr = Param.Bool(False,
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"Determine reset address from kernel entry point if no boot loader")
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highest_el_is_64 = Param.Bool(False,
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"True if the register width of the highest implemented exception level "
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"is 64 bits (ARMv8)")
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phys_addr_range_64 = Param.UInt8(40,
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"Supported physical address range in bits when using AArch64 (ARMv8)")
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have_large_asid_64 = Param.Bool(False,
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"True if ASID is 16 bits in AArch64 (ARMv8)")
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semihosting = Param.ArmSemihosting(NULL,
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"Enable support for the Arm semihosting by settings this parameter")
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m5ops_base = Param.Addr(0,
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"Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 "
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"to disable.")
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def generateDeviceTree(self, state):
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# Generate a device tree root node for the system by creating the root
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# node and adding the generated subnodes of all children.
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# When a child needs to add multiple nodes, this is done by also
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# creating a node called '/' which will then be merged with the
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# root instead of appended.
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def generateMemNode(mem_range):
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node = FdtNode("memory@%x" % long(mem_range.start))
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node.append(FdtPropertyStrings("device_type", ["memory"]))
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node.append(FdtPropertyWords("reg",
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state.addrCells(mem_range.start) +
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state.sizeCells(mem_range.size()) ))
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return node
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root = FdtNode('/')
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root.append(state.addrCellsProperty())
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root.append(state.sizeCellsProperty())
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# Add memory nodes
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for mem_range in self.mem_ranges:
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root.append(generateMemNode(mem_range))
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for node in self.recurseDeviceTree(state):
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# Merge root nodes instead of adding them (for children
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# that need to add multiple root level nodes)
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if node.get_name() == root.get_name():
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root.merge(node)
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else:
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root.append(node)
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return root
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class GenericArmSystem(ArmSystem):
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type = 'GenericArmSystem'
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cxx_header = "arch/arm/system.hh"
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machine_type = Param.ArmMachineType('DTOnly',
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"Machine id from http://www.arm.linux.org.uk/developer/machines/")
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atags_addr = Param.Addr("Address where default atags structure should " \
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"be written")
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dtb_filename = Param.String("",
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"File that contains the Device Tree Blob. Don't use DTB if empty.")
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early_kernel_symbols = Param.Bool(False,
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"enable early kernel symbol tables before MMU")
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enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries")
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panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \
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"guest kernel panics")
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panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \
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"guest kernel oopses")
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class LinuxArmSystem(GenericArmSystem):
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type = 'LinuxArmSystem'
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cxx_header = "arch/arm/linux/system.hh"
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@cxxMethod
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def dumpDmesg(self):
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"""Dump dmesg from the simulated kernel to standard out"""
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pass
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# Have Linux systems for ARM auto-calc their load_addr_mask for proper
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# kernel relocation.
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load_addr_mask = 0x0
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class FreebsdArmSystem(GenericArmSystem):
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type = 'FreebsdArmSystem'
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cxx_header = "arch/arm/freebsd/system.hh"
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