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791092663183bcf01468ca84b6d3c177f0cf7fc7
gem5/src/mem/cache
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Jiasen Huang 7910926631 mem-cache: Set prefetch bit if the blk comes from Prefetch only. 
Original logic setting prefetch inside serviceMSHRTargets
did not exclude the blks that both came from CORE and Prefetch

Change-Id: Iab56b9266eb64baf972b160774aca0823faea458
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54364
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
2021-12-22 01:02:22 +00:00
..
compressors
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
prefetch
mem-cache: Added stats filtering both useful and spanPage prefetch.
2021-12-17 01:04:21 +00:00
replacement_policies
misc: Remove AMD license addition
2021-12-11 04:00:56 +00:00
tags
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
base.cc
mem: Setup stats for Cache hitLatency
2021-11-30 02:59:05 +00:00
base.hh
mem: Setup stats for Cache hitLatency
2021-11-30 02:59:05 +00:00
cache_blk.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
cache_blk.hh
mem-cache: Ensure all fields of the CacheBlk class are initialized.
2021-11-04 22:53:51 +00:00
cache.cc
mem-cache: Set prefetch bit if the blk comes from Prefetch only.
2021-12-22 01:02:22 +00:00
cache.hh
mem,gpu-compute: Stop using the GEM5_NO_DISCARD macro.
2021-07-24 21:57:04 +00:00
Cache.py
mem-cache: add option to send pf on hit on pf
2021-07-09 22:30:45 +00:00
mshr_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mshr_queue.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
mshr.cc
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
mshr.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
noncoherent_cache.cc
mem-cache: Set prefetch bit if the blk comes from Prefetch only.
2021-12-22 01:02:22 +00:00
noncoherent_cache.hh
mem,gpu-compute: Stop using the GEM5_NO_DISCARD macro.
2021-07-24 21:57:04 +00:00
queue_entry.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
queue.hh
misc: Replace type_traits.hh XX::value with XX_v.
2021-07-28 01:48:03 +00:00
SConscript
scons: Add sim_object and enums arguments to SimObject().
2021-12-08 08:01:23 +00:00
write_queue_entry.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
write_queue_entry.hh
misc: Remove sim/cur_tick dependency from sim/core.hh
2021-07-06 09:59:11 +00:00
write_queue.cc
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00
write_queue.hh
misc: Adopt the gem5 namespace
2021-07-01 19:08:24 +00:00