787204c92d
The command executed was `black src configs tests util`. Change-Id: I8dfaa6ab04658fea37618127d6ac19270028d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47024 Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
80 lines
3.4 KiB
Python
80 lines
3.4 KiB
Python
# Copyright (c) 2021 Arm Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2008 The Hewlett-Packard Development Company
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# Copyright (c) 2018 Metempsy Technology Consulting
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.SimObject import SimObject
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class TypeTLB(ScopedEnum):
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"""
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instruction: TLB contains instruction entries only
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data: TLB contains data entries only
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unified: TLB contains both instruction and data entries
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The enum values have been selected in order to perform bitwise
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operations on them. For example a unified TLB contains both
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instruction and data entries so code trying to assess if the
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TLB is storing (e.g.) data entries can do that with:
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bool has_data = tlb->type() & TypeTLB::data;
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"""
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map = {"instruction": 0x1, "data": 0x2, "unified": 0x3}
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class BaseTLB(SimObject):
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type = "BaseTLB"
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abstract = True
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cxx_header = "arch/generic/tlb.hh"
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cxx_class = "gem5::BaseTLB"
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# Ports to connect with other TLB levels
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cpu_side_ports = VectorResponsePort("Ports closer to the CPU side")
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slave = DeprecatedParam(
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cpu_side_ports, "`slave` is now called `cpu_side_ports`"
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)
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mem_side_port = RequestPort("Port closer to memory side")
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master = DeprecatedParam(
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mem_side_port, "`master` is now called `mem_side_port`"
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)
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entry_type = Param.TypeTLB("Instruction/Data/Unified TLB entries")
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next_level = Param.BaseTLB(NULL, "next level")
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