Nilay Vaish 78a72d6972 Config: changes to a couple of error msgs

2012-06-07 08:05:30 -05:00

..

Benchmarks.py

Config: changes to a couple of error msgs

2012-06-07 08:05:30 -05:00

CacheConfig.py

Bus: Split the bus into a non-coherent and coherent bus

2012-05-31 13:30:04 -04:00

Caches.py

O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

2011-12-01 00:15:22 -08:00

cpu2000.py

cpu2000: Add missing art benchmark to all

2012-01-09 18:08:20 -06:00

FSConfig.py

Bus: Split the bus into a non-coherent and coherent bus

2012-05-31 13:30:04 -04:00

O3_ARM_v7a.py

prefetcher: Make prefetcher a sim object instead of it being a parameter on cache

2012-02-12 16:07:38 -06:00

Options.py

Config: Fix help msg for option --mem-size

2012-05-03 05:17:29 -05:00

Simulation.py

Config: Move setWorkCountOptions() to Simulation.py

2012-03-27 18:23:21 -05:00

SysPaths.py

make rcS files read from the m5 source directory, not /dist.

2006-11-08 14:10:25 -05:00