62 lines
2.5 KiB
C++
62 lines
2.5 KiB
C++
/*
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* Copyright .AN) 2007 MIPS Technologies, Inc. All Rights Reserved
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*
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* This software is part of the M5 simulator.
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*
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* THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
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* DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
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* TO THESE TERMS AND CONDITIONS.
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*
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* Permission is granted to use, copy, create derivative works and
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* distribute this software and such derivative works for any purpose,
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* so long as (1) the copyright notice above, this grant of permission,
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* and the disclaimer below appear in all copies and derivative works
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* made, (2) the copyright notice above is augmented as appropriate to
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* reflect the addition of any new copyrightable work in a derivative
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* work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
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* the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
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* advertising or publicity pertaining to the use or distribution of
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* this software without specific, written prior authorization.
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*
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* THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B MIPS MAKES NO WARRANTIES AND
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* DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
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* OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
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* NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
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* IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
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* INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
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* ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
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* THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
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* IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
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* STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
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* POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
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*
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* Authors: Gabe M. Black
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* Korey L. Sewell
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*/
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#ifndef __ARCH_MIPS_SYSCALLRETURN_HH__
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#define __ARCH_MIPS_SYSCALLRETURN_HH__
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#include "sim/syscallreturn.hh"
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#include "cpu/thread_context.hh"
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namespace MipsISA
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{
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static inline void setSyscallReturn(SyscallReturn return_value,
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ThreadContext *tc)
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{
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if (return_value.successful()) {
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// no error
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tc->setIntReg(SyscallSuccessReg, 0);
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tc->setIntReg(ReturnValueReg1, return_value.value());
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} else {
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// got an error, return details
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tc->setIntReg(SyscallSuccessReg, (IntReg) -1);
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tc->setIntReg(ReturnValueReg1, -return_value.value());
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}
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}
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}
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#endif
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