Giacomo Travaglini 7884d5296d arch-arm: Move breakpoint/watchpoint check out of the TLB ...

The breakpoint, watchpoint, vector catch and software step checks
have been moved from the TLB to the SelfDebug class.

This is cleaningup the TLB model which is simply asking the SelfDebug
class if there is a pending debug fault

Change-Id: I1724896b24e4728b32a6b46c5cd51cc6ef279fd7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31079
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

2020-07-13 13:56:41 +00:00

..

arm

arch-arm: Move breakpoint/watchpoint check out of the TLB

2020-07-13 13:56:41 +00:00

gcn3

arch-gcn3: Fix V_MAD_I32_I24 sign extension

2020-06-22 16:14:35 +00:00

generic

sim: Retrofit the VPtr type.

2020-07-04 17:53:54 +00:00

mips

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

null

arch: Delete authors lists from the null arch files.

2020-02-18 03:35:12 +00:00

power

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

riscv

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

sparc

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

x86

arch,cpu: Consolidate most of the StackTrace classes into a base class.

2020-07-11 00:24:38 +00:00

isa_parser.py

arch: list.sort() sorting by key only in python3

2020-03-13 14:24:07 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch,cpu,sim: Eliminate the now empty kernel statistics classes.

2020-06-17 19:54:41 +00:00