Andreas Hansson 77878d0a87 MEM: Prepare mport for master/slave split ...

This patch simplifies the mport in preparation for a split into a
master and slave role for the message ports. In particular,
sendMessageAtomic was only used in a single location and similarly so
sendMessageTiming. The affected interrupt device is updated
accordingly.

2012-02-24 11:50:15 -05:00

..

cmos.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

cmos.hh

x86: Add checkpointing capability to devices

2011-02-06 22:14:18 -08:00

Cmos.py

X86: Move the simulated date in X86_FS forward to 2012.

2009-08-17 20:25:15 -07:00

i8042.cc

MEM: Separate queries for snooping and address ranges

2012-01-17 12:55:09 -06:00

i8042.hh

MEM: Separate queries for snooping and address ranges

2012-01-17 12:55:09 -06:00

i8237.cc

x86: Add checkpointing capability to devices

2011-02-06 22:14:18 -08:00

i8237.hh

x86: Add checkpointing capability to devices

2011-02-06 22:14:18 -08:00

i8254.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

i8254.hh

x86: Add checkpointing capability to devices

2011-02-06 22:14:18 -08:00

i8259.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

i8259.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

i82094aa.cc

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

i82094aa.hh

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

I8042.py

X86: Add some missing default arguments.

2009-02-01 22:40:51 -08:00

I8237.py

X86: Add a dummy minimal DMA controller that doesn't do anything.

2009-01-25 20:35:00 -08:00

I8254.py

X86: Rework interrupt pins to allow one to many connections.

2009-01-31 23:33:54 -08:00

I8259.py

X86: Add some missing default arguments.

2009-02-01 22:40:51 -08:00

I82094AA.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

intdev.cc

MEM: Prepare mport for master/slave split

2012-02-24 11:50:15 -05:00

intdev.hh

MEM: Move port creation to the memory object(s) construction

2012-02-24 11:43:53 -05:00

pc.cc

SE/FS: Remove System::platform and Platform::intrFrequency.

2011-09-30 00:29:07 -07:00

pc.hh

SE/FS: Remove System::platform and Platform::intrFrequency.

2011-09-30 00:29:07 -07:00

Pc.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

PcSpeaker.py

X86: Change I8254 and PCSpeaker devices from subdevices to SimObjects and eliminate subdevices.

2008-10-11 02:16:11 -07:00

SConscript

SE/FS: Build the devices in SE mode.

2011-09-30 00:28:33 -07:00

south_bridge.cc

includes: sort includes again

2009-05-17 14:34:52 -07:00

south_bridge.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

SouthBridge.py

MEM: Introduce the master/slave port roles in the Python classes

2012-02-13 06:43:09 -05:00

speaker.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

speaker.hh

x86: Add checkpointing capability to devices

2011-02-06 22:14:18 -08:00

X86IntPin.py

X86: Rework interrupt pins to allow one to many connections.

2009-01-31 23:33:54 -08:00