740984b30b
Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own. The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures.
616 lines
19 KiB
C++
616 lines
19 KiB
C++
/*
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* Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/intmath.hh"
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#include "debug/RubyCache.hh"
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#include "debug/RubyCacheTrace.hh"
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#include "debug/RubyResourceStalls.hh"
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#include "debug/RubyStats.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/structures/CacheMemory.hh"
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#include "mem/ruby/system/System.hh"
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using namespace std;
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ostream&
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operator<<(ostream& out, const CacheMemory& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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CacheMemory *
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RubyCacheParams::create()
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{
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return new CacheMemory(this);
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}
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CacheMemory::CacheMemory(const Params *p)
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: SimObject(p),
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dataArray(p->dataArrayBanks, p->dataAccessLatency,
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p->start_index_bit, p->ruby_system),
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tagArray(p->tagArrayBanks, p->tagAccessLatency,
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p->start_index_bit, p->ruby_system)
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{
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m_cache_size = p->size;
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m_cache_assoc = p->assoc;
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m_replacementPolicy_ptr = p->replacement_policy;
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m_replacementPolicy_ptr->setCache(this);
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m_start_index_bit = p->start_index_bit;
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m_is_instruction_only_cache = p->is_icache;
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m_resource_stalls = p->resourceStalls;
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}
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void
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CacheMemory::init()
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{
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m_cache_num_sets = (m_cache_size / m_cache_assoc) /
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RubySystem::getBlockSizeBytes();
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assert(m_cache_num_sets > 1);
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m_cache_num_set_bits = floorLog2(m_cache_num_sets);
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assert(m_cache_num_set_bits > 0);
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m_cache.resize(m_cache_num_sets);
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for (int i = 0; i < m_cache_num_sets; i++) {
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m_cache[i].resize(m_cache_assoc);
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for (int j = 0; j < m_cache_assoc; j++) {
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m_cache[i][j] = NULL;
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}
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}
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}
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CacheMemory::~CacheMemory()
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{
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if (m_replacementPolicy_ptr != NULL)
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delete m_replacementPolicy_ptr;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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delete m_cache[i][j];
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}
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}
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}
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// convert a Address to its location in the cache
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int64_t
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CacheMemory::addressToCacheSet(Addr address) const
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{
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assert(address == makeLineAddress(address));
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return bitSelect(address, m_start_index_bit,
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m_start_index_bit + m_cache_num_set_bits - 1);
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int
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CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const
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{
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assert(tag == makeLineAddress(tag));
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// search the set for the tags
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m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
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if (it != m_tag_index.end())
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if (m_cache[cacheSet][it->second]->m_Permission !=
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AccessPermission_NotPresent)
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return it->second;
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return -1; // Not found
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}
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// Given a cache index: returns the index of the tag in a set.
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// returns -1 if the tag is not found.
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int
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CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet,
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Addr tag) const
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{
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assert(tag == makeLineAddress(tag));
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// search the set for the tags
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m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag);
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if (it != m_tag_index.end())
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return it->second;
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return -1; // Not found
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}
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// Given an unique cache block identifier (idx): return the valid address
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// stored by the cache block. If the block is invalid/notpresent, the
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// function returns the 0 address
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Addr
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CacheMemory::getAddressAtIdx(int idx) const
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{
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Addr tmp(0);
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int set = idx / m_cache_assoc;
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assert(set < m_cache_num_sets);
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int way = idx - set * m_cache_assoc;
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assert (way < m_cache_assoc);
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AbstractCacheEntry* entry = m_cache[set][way];
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if (entry == NULL ||
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entry->m_Permission == AccessPermission_Invalid ||
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entry->m_Permission == AccessPermission_NotPresent) {
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return tmp;
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}
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return entry->m_Address;
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}
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bool
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CacheMemory::tryCacheAccess(Addr address, RubyRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == makeLineAddress(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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// Do we even have a tag match?
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AbstractCacheEntry* entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
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data_ptr = &(entry->getDataBlk());
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if (entry->m_Permission == AccessPermission_Read_Write) {
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return true;
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}
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if ((entry->m_Permission == AccessPermission_Read_Only) &&
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(type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
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return true;
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}
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// The line must not be accessible
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}
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data_ptr = NULL;
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return false;
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}
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bool
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CacheMemory::testCacheAccess(Addr address, RubyRequestType type,
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DataBlock*& data_ptr)
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{
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assert(address == makeLineAddress(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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// Do we even have a tag match?
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AbstractCacheEntry* entry = m_cache[cacheSet][loc];
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m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
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data_ptr = &(entry->getDataBlk());
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return m_cache[cacheSet][loc]->m_Permission !=
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AccessPermission_NotPresent;
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}
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data_ptr = NULL;
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return false;
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}
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// tests to see if an address is present in the cache
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bool
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CacheMemory::isTagPresent(Addr address) const
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{
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc == -1) {
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// We didn't find the tag
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DPRINTF(RubyCache, "No tag match for address: %s\n", address);
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return false;
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}
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DPRINTF(RubyCache, "address: %s found\n", address);
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return true;
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}
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// Returns true if there is:
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// a) a tag match on this address or there is
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// b) an unused line in the same cache "way"
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bool
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CacheMemory::cacheAvail(Addr address) const
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{
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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for (int i = 0; i < m_cache_assoc; i++) {
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AbstractCacheEntry* entry = m_cache[cacheSet][i];
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if (entry != NULL) {
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if (entry->m_Address == address ||
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entry->m_Permission == AccessPermission_NotPresent) {
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// Already in the cache or we found an empty entry
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return true;
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}
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} else {
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return true;
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}
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}
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return false;
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}
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AbstractCacheEntry*
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CacheMemory::allocate(Addr address, AbstractCacheEntry *entry, bool touch)
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{
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assert(address == makeLineAddress(address));
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assert(!isTagPresent(address));
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assert(cacheAvail(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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// Find the first open slot
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int64_t cacheSet = addressToCacheSet(address);
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std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet];
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for (int i = 0; i < m_cache_assoc; i++) {
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if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) {
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set[i] = entry; // Init entry
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set[i]->m_Address = address;
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set[i]->m_Permission = AccessPermission_Invalid;
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DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
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address);
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set[i]->m_locked = -1;
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m_tag_index[address] = i;
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entry->setSetIndex(cacheSet);
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entry->setWayIndex(i);
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if (touch) {
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m_replacementPolicy_ptr->touch(cacheSet, i, curTick());
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}
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return entry;
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}
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}
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panic("Allocate didn't find an available entry");
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}
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void
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CacheMemory::deallocate(Addr address)
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{
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assert(address == makeLineAddress(address));
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assert(isTagPresent(address));
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DPRINTF(RubyCache, "address: %s\n", address);
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if (loc != -1) {
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delete m_cache[cacheSet][loc];
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m_cache[cacheSet][loc] = NULL;
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m_tag_index.erase(address);
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}
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}
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// Returns with the physical address of the conflicting cache line
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Addr
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CacheMemory::cacheProbe(Addr address) const
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{
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assert(address == makeLineAddress(address));
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assert(!cacheAvail(address));
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int64_t cacheSet = addressToCacheSet(address);
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return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]->
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m_Address;
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}
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// looks an address up in the cache
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AbstractCacheEntry*
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CacheMemory::lookup(Addr address)
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{
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc == -1) return NULL;
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return m_cache[cacheSet][loc];
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}
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// looks an address up in the cache
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const AbstractCacheEntry*
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CacheMemory::lookup(Addr address) const
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{
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc == -1) return NULL;
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return m_cache[cacheSet][loc];
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}
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// Sets the most recently used bit for a cache block
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void
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CacheMemory::setMRU(Addr address)
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{
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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if(loc != -1)
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m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
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}
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void
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CacheMemory::setMRU(const AbstractCacheEntry *e)
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{
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uint32_t cacheSet = e->getSetIndex();
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uint32_t loc = e->getWayIndex();
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m_replacementPolicy_ptr->touch(cacheSet, loc, curTick());
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}
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void
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CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const
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{
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uint64_t warmedUpBlocks = 0;
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uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets *
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(uint64_t)m_cache_assoc;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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if (m_cache[i][j] != NULL) {
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AccessPermission perm = m_cache[i][j]->m_Permission;
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RubyRequestType request_type = RubyRequestType_NULL;
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if (perm == AccessPermission_Read_Only) {
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if (m_is_instruction_only_cache) {
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request_type = RubyRequestType_IFETCH;
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} else {
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request_type = RubyRequestType_LD;
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}
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} else if (perm == AccessPermission_Read_Write) {
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request_type = RubyRequestType_ST;
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}
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if (request_type != RubyRequestType_NULL) {
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tr->addRecord(cntrl, m_cache[i][j]->m_Address,
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0, request_type,
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m_replacementPolicy_ptr->getLastAccess(i, j),
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m_cache[i][j]->getDataBlk());
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warmedUpBlocks++;
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}
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}
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}
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}
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DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks"
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"recorded %.2f%% \n", name().c_str(), warmedUpBlocks,
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totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0);
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}
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void
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CacheMemory::print(ostream& out) const
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{
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out << "Cache dump: " << name() << endl;
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for (int i = 0; i < m_cache_num_sets; i++) {
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for (int j = 0; j < m_cache_assoc; j++) {
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if (m_cache[i][j] != NULL) {
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out << " Index: " << i
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<< " way: " << j
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<< " entry: " << *m_cache[i][j] << endl;
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} else {
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out << " Index: " << i
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<< " way: " << j
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<< " entry: NULL" << endl;
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}
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}
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}
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}
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void
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CacheMemory::printData(ostream& out) const
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{
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out << "printData() not supported" << endl;
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}
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void
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CacheMemory::setLocked(Addr address, int context)
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{
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DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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m_cache[cacheSet][loc]->setLocked(context);
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}
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void
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CacheMemory::clearLocked(Addr address)
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{
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DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address);
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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m_cache[cacheSet][loc]->clearLocked();
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}
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bool
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CacheMemory::isLocked(Addr address, int context)
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{
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assert(address == makeLineAddress(address));
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int64_t cacheSet = addressToCacheSet(address);
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int loc = findTagInSet(cacheSet, address);
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assert(loc != -1);
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DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
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address, m_cache[cacheSet][loc]->m_locked, context);
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return m_cache[cacheSet][loc]->isLocked(context);
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}
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void
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CacheMemory::regStats()
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{
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m_demand_hits
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.name(name() + ".demand_hits")
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.desc("Number of cache demand hits")
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;
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m_demand_misses
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.name(name() + ".demand_misses")
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.desc("Number of cache demand misses")
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;
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m_demand_accesses
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.name(name() + ".demand_accesses")
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.desc("Number of cache demand accesses")
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;
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m_demand_accesses = m_demand_hits + m_demand_misses;
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m_sw_prefetches
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.name(name() + ".total_sw_prefetches")
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.desc("Number of software prefetches")
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.flags(Stats::nozero)
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;
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m_hw_prefetches
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.name(name() + ".total_hw_prefetches")
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.desc("Number of hardware prefetches")
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.flags(Stats::nozero)
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;
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m_prefetches
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.name(name() + ".total_prefetches")
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.desc("Number of prefetches")
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.flags(Stats::nozero)
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;
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m_prefetches = m_sw_prefetches + m_hw_prefetches;
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m_accessModeType
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.init(RubyRequestType_NUM)
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.name(name() + ".access_mode")
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.flags(Stats::pdf | Stats::total)
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;
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for (int i = 0; i < RubyAccessMode_NUM; i++) {
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m_accessModeType
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.subname(i, RubyAccessMode_to_string(RubyAccessMode(i)))
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.flags(Stats::nozero)
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;
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}
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numDataArrayReads
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.name(name() + ".num_data_array_reads")
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.desc("number of data array reads")
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.flags(Stats::nozero)
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;
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numDataArrayWrites
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.name(name() + ".num_data_array_writes")
|
|
.desc("number of data array writes")
|
|
.flags(Stats::nozero)
|
|
;
|
|
|
|
numTagArrayReads
|
|
.name(name() + ".num_tag_array_reads")
|
|
.desc("number of tag array reads")
|
|
.flags(Stats::nozero)
|
|
;
|
|
|
|
numTagArrayWrites
|
|
.name(name() + ".num_tag_array_writes")
|
|
.desc("number of tag array writes")
|
|
.flags(Stats::nozero)
|
|
;
|
|
|
|
numTagArrayStalls
|
|
.name(name() + ".num_tag_array_stalls")
|
|
.desc("number of stalls caused by tag array")
|
|
.flags(Stats::nozero)
|
|
;
|
|
|
|
numDataArrayStalls
|
|
.name(name() + ".num_data_array_stalls")
|
|
.desc("number of stalls caused by data array")
|
|
.flags(Stats::nozero)
|
|
;
|
|
}
|
|
|
|
// assumption: SLICC generated files will only call this function
|
|
// once **all** resources are granted
|
|
void
|
|
CacheMemory::recordRequestType(CacheRequestType requestType, Addr addr)
|
|
{
|
|
DPRINTF(RubyStats, "Recorded statistic: %s\n",
|
|
CacheRequestType_to_string(requestType));
|
|
switch(requestType) {
|
|
case CacheRequestType_DataArrayRead:
|
|
if (m_resource_stalls)
|
|
dataArray.reserve(addressToCacheSet(addr));
|
|
numDataArrayReads++;
|
|
return;
|
|
case CacheRequestType_DataArrayWrite:
|
|
if (m_resource_stalls)
|
|
dataArray.reserve(addressToCacheSet(addr));
|
|
numDataArrayWrites++;
|
|
return;
|
|
case CacheRequestType_TagArrayRead:
|
|
if (m_resource_stalls)
|
|
tagArray.reserve(addressToCacheSet(addr));
|
|
numTagArrayReads++;
|
|
return;
|
|
case CacheRequestType_TagArrayWrite:
|
|
if (m_resource_stalls)
|
|
tagArray.reserve(addressToCacheSet(addr));
|
|
numTagArrayWrites++;
|
|
return;
|
|
default:
|
|
warn("CacheMemory access_type not found: %s",
|
|
CacheRequestType_to_string(requestType));
|
|
}
|
|
}
|
|
|
|
bool
|
|
CacheMemory::checkResourceAvailable(CacheResourceType res, Addr addr)
|
|
{
|
|
if (!m_resource_stalls) {
|
|
return true;
|
|
}
|
|
|
|
if (res == CacheResourceType_TagArray) {
|
|
if (tagArray.tryAccess(addressToCacheSet(addr))) return true;
|
|
else {
|
|
DPRINTF(RubyResourceStalls,
|
|
"Tag array stall on addr %s in set %d\n",
|
|
addr, addressToCacheSet(addr));
|
|
numTagArrayStalls++;
|
|
return false;
|
|
}
|
|
} else if (res == CacheResourceType_DataArray) {
|
|
if (dataArray.tryAccess(addressToCacheSet(addr))) return true;
|
|
else {
|
|
DPRINTF(RubyResourceStalls,
|
|
"Data array stall on addr %s in set %d\n",
|
|
addr, addressToCacheSet(addr));
|
|
numDataArrayStalls++;
|
|
return false;
|
|
}
|
|
} else {
|
|
assert(false);
|
|
return true;
|
|
}
|
|
}
|
|
|
|
bool
|
|
CacheMemory::isBlockInvalid(int64_t cache_set, int64_t loc)
|
|
{
|
|
return (m_cache[cache_set][loc]->m_Permission == AccessPermission_Invalid);
|
|
}
|
|
|
|
bool
|
|
CacheMemory::isBlockNotBusy(int64_t cache_set, int64_t loc)
|
|
{
|
|
return (m_cache[cache_set][loc]->m_Permission != AccessPermission_Busy);
|
|
}
|