Giacomo Travaglini 735cf323b5 arch-arm: Fix XN in TLB permissions ...

The SIF condition check should be logically ORed with the TLB
entry XN attribute, instead of overriding it.

Change-Id: I70b38d97bbdc82b9f385d40ad06546785fc2c5bb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32635
Tested-by: kokoro <noreply+kokoro@google.com>

2020-08-14 13:07:41 +00:00

..

arm

arch-arm: Fix XN in TLB permissions

2020-08-14 13:07:41 +00:00

gcn3

arch-gcn3: Free registers when execMask = 0

2020-08-13 19:39:34 +00:00

generic

sim: Retrofit the VPtr type.

2020-07-04 17:53:54 +00:00

mips

arch-mips: Remove old TypeBufferArg call

2020-08-08 17:15:21 +00:00

null

arch: Delete authors lists from the null arch files.

2020-02-18 03:35:12 +00:00

power

arch-power: Implement GDB XML target description for PowerPC

2020-08-06 15:16:03 +00:00

riscv

arch: Use VPtr for uname.

2020-08-05 23:52:25 +00:00

sparc

arch: Use VPtr for uname.

2020-08-05 23:52:25 +00:00

x86

arch: Use VPtr for uname.

2020-08-05 23:52:25 +00:00

isa_parser.py

arch: list.sort() sorting by key only in python3

2020-03-13 14:24:07 +00:00

micro_asm_test.py

arch: Delete authors lists from generic arch files.

2020-02-18 03:34:56 +00:00

micro_asm.py

misc: Make exception handling python3 compliant

2020-03-13 14:24:07 +00:00

SConscript

arch: Remove the stacktrace.hh switching header file.

2020-08-12 06:19:24 +00:00