Ali Saidi 7359e2df01 implement the Tcc instruction to call syscall. ...

arch/sparc/isa/bitfields.isa:
    the trap field is 7:0
arch/sparc/isa/decoder.isa:
    add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
    We need the syscall num register

--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a

2006-03-15 18:12:01 -05:00

..

alpha

add translations for new sections that are mmapped or when the brk

2006-03-15 17:04:50 -05:00

mips

add translations for new sections that are mmapped or when the brk

2006-03-15 17:04:50 -05:00

sparc

implement the Tcc instruction to call syscall.

2006-03-15 18:12:01 -05:00

isa_parser.py

Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.

2006-03-14 15:55:00 -05:00

isa_specific.hh

Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu

2006-03-14 18:28:51 -05:00

SConscript

Moved registerfile.hh to regfile.hh

2006-03-14 16:05:44 -05:00