This patch syncs the DRAMPower library of gem5 to the external github (https://github.com/ravenrd/DRAMPower). The version pulled in is the commit: 90d6290f802c29b3de9e10233ceee22290907ce6 from 30th Oct. 2016. This change also modifies the DRAM Ctrl interaction with the DRAMPower, due to changes in the lib API in the above version. Previously multiple functions were called to prepare the power lib before calling the function that would calculate the enery. With the new API, these functions are encompassed inside the function to calculate the energy and therefore should now be removed from the DRAM controller. The other key difference is the introduction of a new function called calcWindowEnergy which can be useful for any system that wants to do measurements over intervals. For gem5 DRAM ctrl that means we now need to accumulate the window energy measurements into the total stat. Change-Id: I3570fff2805962e166ff2a1a3217ebf2d5a197fb Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5724 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
295 lines
10 KiB
C++
295 lines
10 KiB
C++
/*
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* Copyright (c) 2012-2014, TU Delft
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* Copyright (c) 2012-2014, TU Eindhoven
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* Copyright (c) 2012-2014, TU Kaiserslautern
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Karthik Chandrasekar,
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* Matthias Jung,
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* Omar Naji,
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* Sven Goossens,
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* Éder F. Zulian
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* Subash Kannoth
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* Felipe S. Prado
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*
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*/
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#include <fstream>
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#include <algorithm>
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#include <sstream>
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#include "CommandAnalysis.h"
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#include "CmdScheduler.h"
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using namespace Data;
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using namespace std;
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bool commandSorter(const MemCommand& i, const MemCommand& j)
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{
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if (i.getTimeInt64() == j.getTimeInt64()) {
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return i.getType() == MemCommand::PRE && j.getType() != MemCommand::PRE;
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} else {
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return i.getTimeInt64() < j.getTimeInt64();
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}
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}
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CommandAnalysis::CommandAnalysis(const Data::MemorySpecification& memSpec) :
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memSpec(memSpec)
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{
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auto &nBanks = memSpec.memArchSpec.nbrOfBanks;
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// Initializing all counters and variables
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numberofactsBanks.assign(static_cast<size_t>(nBanks), 0);
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numberofpresBanks.assign(static_cast<size_t>(nBanks), 0);
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numberofreadsBanks.assign(static_cast<size_t>(nBanks), 0);
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numberofwritesBanks.assign(static_cast<size_t>(nBanks), 0);
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actcyclesBanks.assign(static_cast<size_t>(nBanks), 0);
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numberofrefbBanks.assign(static_cast<size_t>(nBanks), 0);
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first_act_cycle_banks.resize(static_cast<size_t>(nBanks), 0);
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clearStats(0);
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zero = 0;
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bank_state.resize(static_cast<size_t>(nBanks), BANK_PRECHARGED);
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last_bank_state.resize(static_cast<size_t>(nBanks), BANK_PRECHARGED);
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mem_state = MS_NOT_IN_PD;
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cmd_list.clear();
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cached_cmd.clear();
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activation_cycle.resize(static_cast<size_t>(nBanks), 0);
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num_banks = nBanks;
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}
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// function to clear counters
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void CommandAnalysis::clearStats(const int64_t timestamp)
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{
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std::fill(numberofactsBanks.begin(), numberofactsBanks.end(), 0);
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std::fill(numberofpresBanks.begin(), numberofpresBanks.end(), 0);
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std::fill(numberofreadsBanks.begin(), numberofreadsBanks.end(), 0);
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std::fill(numberofwritesBanks.begin(), numberofwritesBanks.end(), 0);
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std::fill(actcyclesBanks.begin(), actcyclesBanks.end(), 0);
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numberofrefs = 0;
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f_act_pdns = 0;
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s_act_pdns = 0;
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f_pre_pdns = 0;
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s_pre_pdns = 0;
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numberofsrefs = 0;
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actcycles = 0;
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precycles = 0;
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f_act_pdcycles = 0;
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s_act_pdcycles = 0;
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f_pre_pdcycles = 0;
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s_pre_pdcycles = 0;
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pup_act_cycles = 0;
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pup_pre_cycles = 0;
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sref_cycles = 0;
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spup_cycles = 0;
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sref_ref_act_cycles = 0;
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sref_ref_pre_cycles = 0;
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spup_ref_act_cycles = 0;
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spup_ref_pre_cycles = 0;
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idlecycles_act = 0;
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idlecycles_pre = 0;
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// reset count references to timestamp so that they are moved
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// to start of next stats generation
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std::fill(first_act_cycle_banks.begin(), first_act_cycle_banks.end(), timestamp);
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first_act_cycle = timestamp;
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pdn_cycle = timestamp;
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sref_cycle_window = timestamp;
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end_act_op = timestamp;
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end_read_op = timestamp;
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end_write_op = timestamp;
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latest_read_cycle = -1;
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latest_write_cycle = -1;
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if (timestamp == 0) {
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latest_pre_cycle = -1;
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latest_act_cycle = -1;
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sref_cycle = 0;
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last_pre_cycle = 0;
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sref_ref_act_cycles_window = 0;
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sref_ref_pre_cycles_window = 0;
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} else {
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last_pre_cycle = max(timestamp,last_pre_cycle);
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latest_pre_cycle = max(timestamp, latest_pre_cycle);
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if (latest_act_cycle < timestamp)
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latest_act_cycle = -1;
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}
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}
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// function to clear all arrays
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void CommandAnalysis::clear()
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{
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cached_cmd.clear();
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cmd_list.clear();
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last_bank_state.clear();
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bank_state.clear();
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}
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// Reads through the trace file, identifies the timestamp, command and bank
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// If the issued command includes an auto-precharge, adds an explicit
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// precharge to a cached command list and computes the precharge offset from the
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// issued command timestamp, when the auto-precharge would kick in
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void CommandAnalysis::getCommands(std::vector<MemCommand>& list, bool lastupdate, int64_t timestamp)
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{
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if (!next_window_cmd_list.empty()) {
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list.insert(list.begin(), next_window_cmd_list.begin(), next_window_cmd_list.end());
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next_window_cmd_list.clear();
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}
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for (size_t i = 0; i < list.size(); ++i) {
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MemCommand& cmd = list[i];
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MemCommand::cmds cmdType = cmd.getType();
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if (cmdType == MemCommand::ACT) {
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activation_cycle[cmd.getBank()] = cmd.getTimeInt64();
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} else if (cmdType == MemCommand::RDA || cmdType == MemCommand::WRA) {
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// Remove auto-precharge flag from command
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cmd.setType(cmd.typeWithoutAutoPrechargeFlag());
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// Add the auto precharge to the list of cached_cmds
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int64_t preTime = max(cmd.getTimeInt64() + cmd.getPrechargeOffset(memSpec, cmdType),
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activation_cycle[cmd.getBank()] + memSpec.memTimingSpec.RAS);
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list.push_back(MemCommand(MemCommand::PRE, cmd.getBank(), preTime));
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}
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if (!lastupdate && timestamp > 0) {
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if(cmd.getTimeInt64() > timestamp)
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{
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MemCommand nextWindowCmd = list[i];
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next_window_cmd_list.push_back(nextWindowCmd);
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list.erase(find(list.begin(), list.end(), cmd));
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}
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}
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}
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sort(list.begin(), list.end(), commandSorter);
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if (lastupdate && list.empty() == false) {
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// Add cycles at the end of the list
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int64_t t = timeToCompletion(list.back().getType()) + list.back().getTimeInt64() - 1;
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list.push_back(MemCommand(MemCommand::NOP, 0, t));
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}
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evaluateCommands(list);
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} // CommandAnalysis::getCommands
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// Used to analyse a given list of commands and identify command timings
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// and memory state transitions
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void CommandAnalysis::evaluateCommands(vector<MemCommand>& cmd_list)
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{
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// for each command identify timestamp, type and bank
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for (auto cmd : cmd_list) {
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// For command type
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int type = cmd.getType();
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// For command bank
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unsigned bank = cmd.getBank();
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// Command Issue timestamp in clock cycles (cc)
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int64_t timestamp = cmd.getTimeInt64();
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if (type == MemCommand::ACT) {
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handleAct(bank, timestamp);
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} else if (type == MemCommand::RD) {
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handleRd(bank, timestamp);
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} else if (type == MemCommand::WR) {
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handleWr(bank, timestamp);
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} else if (type == MemCommand::REF) {
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handleRef(bank, timestamp);
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} else if (type == MemCommand::REFB) {
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handleRefB(bank, timestamp);
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} else if (type == MemCommand::PRE) {
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handlePre(bank, timestamp);
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} else if (type == MemCommand::PREA) {
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handlePreA(bank, timestamp);
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} else if (type == MemCommand::PDN_F_ACT) {
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handlePdnFAct(bank, timestamp);
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} else if (type == MemCommand::PDN_S_ACT) {
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handlePdnSAct(bank, timestamp);
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} else if (type == MemCommand::PDN_F_PRE) {
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handlePdnFPre(bank, timestamp);
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} else if (type == MemCommand::PDN_S_PRE) {
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handlePdnSPre(bank, timestamp);
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} else if (type == MemCommand::PUP_ACT) {
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handlePupAct(timestamp);
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} else if (type == MemCommand::PUP_PRE) {
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handlePupPre(timestamp);
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} else if (type == MemCommand::SREN) {
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handleSREn(bank, timestamp);
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} else if (type == MemCommand::SREX) {
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handleSREx(bank, timestamp);
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} else if (type == MemCommand::END || type == MemCommand::NOP) {
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handleNopEnd(timestamp);
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} else {
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printWarning("Unknown command given, exiting.", type, timestamp, bank);
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exit(-1);
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}
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}
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} // CommandAnalysis::evaluateCommands
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// To update idle period information whenever active cycles may be idle
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void CommandAnalysis::idle_act_update(int64_t latest_read_cycle, int64_t latest_write_cycle,
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int64_t latest_act_cycle, int64_t timestamp)
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{
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if (latest_read_cycle >= 0) {
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end_read_op = latest_read_cycle + timeToCompletion(MemCommand::RD) - 1;
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}
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if (latest_write_cycle >= 0) {
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end_write_op = latest_write_cycle + timeToCompletion(MemCommand::WR) - 1;
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}
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if (latest_act_cycle >= 0) {
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end_act_op = latest_act_cycle + timeToCompletion(MemCommand::ACT) - 1;
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}
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idlecycles_act += max(zero, timestamp - max(max(end_read_op, end_write_op),
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end_act_op));
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} // CommandAnalysis::idle_act_update
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// To update idle period information whenever precharged cycles may be idle
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void CommandAnalysis::idle_pre_update(int64_t timestamp, int64_t latest_pre_cycle)
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{
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if (latest_pre_cycle > 0) {
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idlecycles_pre += max(zero, timestamp - latest_pre_cycle -
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memSpec.memTimingSpec.RP);
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} else if (latest_pre_cycle == 0) {
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idlecycles_pre += max(zero, timestamp - latest_pre_cycle);
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}
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}
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