Tuan Ta 72d1d2930f arch-riscv: initialize RISC-V's thread pointer register in clone syscall ...

This patch initializes thread pointer register to Thread Local Storage
(TLS)'s pointer given to a clone system call.

Change-Id: I03e2cf4763e6a0ed31f357772a513a05e1e3461b
Reviewed-on: https://gem5-review.googlesource.com/c/9622
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

2019-02-08 15:25:30 +00:00

..

linux.cc

arch-riscv: Enable support for riscv 32-bit in SE mode.

2019-02-07 01:48:08 +00:00

linux.hh

arch-riscv: initialize RISC-V's thread pointer register in clone syscall

2019-02-08 15:25:30 +00:00

process.cc

arch-riscv: Enable support for riscv 32-bit in SE mode.

2019-02-07 01:48:08 +00:00

process.hh

arch-riscv: Enable support for riscv 32-bit in SE mode.

2019-02-07 01:48:08 +00:00