716e447da8
including IPR accesses and store-conditionals. These class of instructions will not execute correctly in a superscalar machine
248 lines
9.6 KiB
C++
248 lines
9.6 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <list>
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#include <vector>
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#include "cpu/inorder/resources/execution_unit.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "debug/InOrderExecute.hh"
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#include "debug/InOrderStall.hh"
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using namespace std;
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using namespace ThePipeline;
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ExecutionUnit::ExecutionUnit(string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu,
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ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu),
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lastExecuteTick(0), lastControlTick(0)
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{ }
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void
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ExecutionUnit::regStats()
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{
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predictedTakenIncorrect
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.name(name() + ".predictedTakenIncorrect")
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.desc("Number of Branches Incorrectly Predicted As Taken.");
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predictedNotTakenIncorrect
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.name(name() + ".predictedNotTakenIncorrect")
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.desc("Number of Branches Incorrectly Predicted As Not Taken).");
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executions
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.name(name() + ".executions")
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.desc("Number of Instructions Executed.");
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predictedIncorrect
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.name(name() + ".mispredicted")
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.desc("Number of Branches Incorrectly Predicted");
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predictedCorrect
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.name(name() + ".predicted")
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.desc("Number of Branches Incorrectly Predicted");
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mispredictPct
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.name(name() + ".mispredictPct")
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.desc("Percentage of Incorrect Branches Predicts")
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.precision(6);
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mispredictPct = (predictedIncorrect /
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(predictedCorrect + predictedIncorrect)) * 100;
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Resource::regStats();
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}
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void
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ExecutionUnit::execute(int slot_num)
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{
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ResourceRequest* exec_req = reqs[slot_num];
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DynInstPtr inst = reqs[slot_num]->inst;
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if (inst->fault != NoFault) {
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DPRINTF(InOrderExecute,
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"[tid:%i]: [sn:%i]: Detected %s fault @ %x. Forwarding to "
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"next stage.\n", inst->readTid(), inst->seqNum, inst->fault->name(),
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inst->pcState());
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exec_req->done();
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return;
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}
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Fault fault = NoFault;
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Tick cur_tick = curTick();
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unsigned stage_num = exec_req->getStageNum();
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ThreadID tid = inst->readTid();
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#if TRACING_ON
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InstSeqNum seq_num = inst->seqNum;
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#endif
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switch (exec_req->cmd)
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{
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case ExecuteInst:
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{
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if (inst->isNop()) {
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DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] [PC:%s] Ignoring execution"
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"of %s.\n", inst->readTid(), seq_num, inst->pcState(),
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inst->instName());
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inst->setExecuted();
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exec_req->done();
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return;
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} else {
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DPRINTF(InOrderExecute, "[tid:%i] Executing [sn:%i] [PC:%s] %s.\n",
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inst->readTid(), seq_num, inst->pcState(), inst->instName());
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}
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if (cur_tick != lastExecuteTick) {
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lastExecuteTick = cur_tick;
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}
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//@todo: handle address generation here
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assert(!inst->isMemRef());
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if (inst->isControl()) {
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if (lastControlTick == cur_tick) {
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DPRINTF(InOrderExecute, "Can not Execute More than One Control "
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"Inst Per Cycle. Blocking Request.\n");
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exec_req->done(false);
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return;
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}
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lastControlTick = curTick();
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// Evaluate Branch
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fault = inst->execute();
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// Should unconditional control , pc relative count as an
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// execution??? Probably not.
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executions++;
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if (fault == NoFault) {
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inst->setExecuted();
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if (inst->mispredicted()) {
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assert(inst->isControl());
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// Set up Squash Generated By this Misprediction
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TheISA::PCState pc = inst->pcState();
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TheISA::advancePC(pc, inst->staticInst);
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inst->setPredTarg(pc);
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inst->setSquashInfo(stage_num);
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setupSquash(inst, stage_num, tid);
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i] Squashing from "
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"stage %i. Redirecting fetch to %s.\n", tid,
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inst->seqNum, stage_num, pc);
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DPRINTF(InOrderStall, "STALL: [tid:%i]: Branch"
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" misprediction at %s\n", tid, inst->pcState());
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if (inst->predTaken()) {
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predictedTakenIncorrect++;
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DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
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"PC %s ... Mispredicts! "
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"(Prediction: Taken)\n",
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tid, inst->seqNum,
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inst->staticInst->disassemble(
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inst->instAddr()),
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inst->pcState());
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} else {
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predictedNotTakenIncorrect++;
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DPRINTF(InOrderExecute, "[tid:%i] [sn:%i] %s ..."
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"PC %s ... Mispredicts! "
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"(Prediction: Not Taken)\n",
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tid, inst->seqNum,
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inst->staticInst->disassemble(
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inst->instAddr()),
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inst->pcState());
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}
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predictedIncorrect++;
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} else {
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Prediction"
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"Correct.\n", inst->readTid(), seq_num);
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predictedCorrect++;
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}
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exec_req->done();
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} else {
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DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
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inst->readTid(), inst->seqNum, fault->name());
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inst->fault = fault;
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exec_req->done();
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}
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} else {
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// Regular ALU instruction
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fault = inst->execute();
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executions++;
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if (fault == NoFault) {
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inst->setExecuted();
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#if TRACING_ON
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for (int didx = 0; didx < inst->numDestRegs(); didx++)
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if (inst->resultType(didx) == InOrderDynInst::Float ||
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inst->resultType(didx) == InOrderDynInst::FloatBits ||
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inst->resultType(didx) == InOrderDynInst::Double)
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
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"of FP execution is %08f (%x).\n", inst->readTid(),
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seq_num, didx, inst->readFloatResult(didx),
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inst->readFloatBitsResult(didx));
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else
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: Dest result %i "
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"of Int execution is 0x%x.\n", inst->readTid(),
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seq_num, didx, inst->readIntResult(didx));
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#endif
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#if !FULL_SYSTEM
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// The Syscall might change the PC, so conservatively
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// squash everything behing it
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if (inst->isSyscall()) {
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inst->setSquashInfo(stage_num);
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setupSquash(inst, stage_num, tid);
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}
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#endif
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} else {
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DPRINTF(InOrderExecute, "[tid:%i]: [sn:%i]: had a %s "
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"fault.\n", inst->readTid(), seq_num, fault->name());
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DPRINTF(Fault, "[tid:%i]:[sn:%i]: Fault %s found\n",
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inst->readTid(), inst->seqNum, fault->name());
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inst->fault = fault;
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}
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exec_req->done();
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}
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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}
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