Change-Id: I2a165d3130c1464a73823046e4c7b03ba0355459 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25457 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
161 lines
5.9 KiB
C++
161 lines
5.9 KiB
C++
/*
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* Copyright (c) 2014 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* Copyright (c) 2013 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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*
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* Defines an sc_module type to wrap a gem5 simulation. The 'evaluate'
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* thread on that module implements the gem5 event loop.
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*
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* This currently only supports a single event queue and strictly
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* cooperatively threaded SystemC threads and so there should be at
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* most one Gem5Module instantiated in any simulation.
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*/
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#ifndef __SIM_SC_MODULE_HH__
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#define __SIM_SC_MODULE_HH__
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#include <systemc>
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#include "sim/eventq.hh"
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#include "sim/sim_events.hh"
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namespace Gem5SystemC
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{
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/** A SystemC module implementing the gem5 event queue. This object
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* doesn't actually own any of the simulation SimObjects (those need
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* to be administered separately) but it does control the event
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* queue.
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*
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* The event loop here services gem5 events in order at the current time
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* and then yielding to another SystemC thread. gem5 events are not
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* individually scheduled in SystemC. For this reason, asynchronous events
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* and function interaction (for example TLM) with gem5 from SystemC must
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* notify the module so that the yielding 'wait' can be interrupted.
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* From the point of view of another SystemC module calling into gem5,
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* curTick can lag SystemC time, be exactly the same time but *never*
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* lead SystemC time.
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*
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* This functionality is wrapped in an sc_module as its intended that
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* the a class representing top level simulation control should be derived
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* from this class. */
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class Module : public sc_core::sc_channel
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{
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protected:
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/** Event to trigger (via. ::notify) for event scheduling from
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* outside gem5 */
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sc_core::sc_event externalSchedulingEvent;
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/** Event to trigger on exit of eventLoop */
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sc_core::sc_event eventLoopExitEvent;
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/** Event to trigger to enter eventLoop */
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sc_core::sc_event eventLoopEnterEvent;
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/** Expected exit time of last eventLoop sleep */
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Tick wait_exit_time;
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/** Are we in Module::simulate? Used to mask events when not inside
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* the simulate loop */
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bool in_simulate;
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/** Placeholder base class for a variant event queue if this becomes
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* useful */
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class SCEventQueue : public EventQueue
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{
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protected:
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Module &module;
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public:
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SCEventQueue(const std::string &name,
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Module &module_) : EventQueue(name), module(module_)
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{ }
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/** Signal module to wakeup */
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void wakeup(Tick when);
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};
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/** Service any async event marked up in the globals event_... */
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void serviceAsyncEvent();
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public:
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/** Simulate is a process */
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SC_HAS_PROCESS(Module);
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Module(sc_core::sc_module_name name);
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/** Last exitEvent from eventLoop */
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Event *exitEvent;
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/** Setup global event queues. Call this before any other event queues
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* are created */
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static void setupEventQueues(Module &module);
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/** Catch gem5 time up with SystemC */
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void catchup();
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/** Notify an externalSchedulingEvent at the given time from the
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* current SystemC time */
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void notify(sc_core::sc_time time_from_now = sc_core::SC_ZERO_TIME);
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/** Process an event triggered by externalSchedulingEvent and also
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* call eventLoop (to try and mop up any events at this time) if there
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* are any scheduled events */
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void serviceExternalEvent();
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/** Process gem5 events up until an exit event or there are no events
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* left. */
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void eventLoop();
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/** Run eventLoop up to num_cycles and return the final event */
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GlobalSimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
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};
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/** There are assumptions throughout Gem5SystemC file that a tick is 1ps.
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* Make this the case */
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void setTickFrequency();
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}
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#endif // __SIM_SC_MODULE_HH__
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