6a44472b1c
As noted here: https://gem5.atlassian.net/browse/GEM5-1133, NVMInterface.py does not have a `controller()` function, which is used by `configs/common/MemConfig.py` to obtain a memory controller for a specific memory type selected. This patch adds a `controller()` function to `NVNInterface.py` to avoid the reported error. It should be noted that we do not enforce a rule that a memory type must include a `controller()` function. `se.py`, and other scrips that use `configs/common/MemConfigs.py`, should not rely on this false assumption. Change-Id: Ieba62f803d3b9f9c5c3c863d5a8c4ca16c5e5e82 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54923 Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu> Maintainer: Bobby Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
116 lines
4.5 KiB
Python
116 lines
4.5 KiB
Python
# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.MemCtrl import MemCtrl
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from m5.objects.MemInterface import MemInterface
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from m5.objects.DRAMInterface import AddrMap
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# The following interface aims to model byte-addressable NVM
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# The most important system-level performance effects of a NVM
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# are modeled without getting into too much detail of the media itself.
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class NVMInterface(MemInterface):
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type = 'NVMInterface'
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cxx_header = "mem/mem_interface.hh"
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cxx_class = 'gem5::memory::NVMInterface'
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# NVM DIMM could have write buffer to offload writes
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# define buffer depth, which will limit the number of pending writes
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max_pending_writes = Param.Unsigned("1", "Max pending write commands")
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# NVM DIMM could have buffer to offload read commands
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# define buffer depth, which will limit the number of pending reads
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max_pending_reads = Param.Unsigned("1", "Max pending read commands")
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# timing behaviour and constraints - all in nanoseconds
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# define average latency for NVM media. Latency defined uniquely
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# for read and writes as the media is typically not symmetric
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tREAD = Param.Latency("100ns", "Average NVM read latency")
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tWRITE = Param.Latency("200ns", "Average NVM write latency")
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tSEND = Param.Latency("15ns", "Access latency")
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two_cycle_rdwr = Param.Bool(False,
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"Two cycles required to send read and write commands")
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def controller(self):
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"""
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Instantiate the memory controller and bind it to
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the current interface.
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"""
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controller = MemCtrl()
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controller.nvm = self
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return controller
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# NVM delays and device architecture defined to mimic PCM like memory.
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# Can be configured with DDR4_2400 sharing the channel
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class NVM_2400_1x64(NVMInterface):
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write_buffer_size = 128
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read_buffer_size = 64
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max_pending_writes = 128
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max_pending_reads = 64
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device_rowbuffer_size = '256B'
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# 8X capacity compared to DDR4 x4 DIMM with 8Gb devices
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device_size = '512GiB'
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# Mimic 64-bit media agnostic DIMM interface
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device_bus_width = 64
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devices_per_rank = 1
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ranks_per_channel = 1
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banks_per_rank = 16
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burst_length = 8
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two_cycle_rdwr = True
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# 1200 MHz
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tCK = '0.833ns'
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tREAD = '150ns'
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tWRITE = '500ns';
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tSEND = '14.16ns';
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tBURST = '3.332ns';
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# Default all bus turnaround and rank bus delay to 2 cycles
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# With DDR data bus, clock = 1200 MHz = 1.666 ns
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tWTR = '1.666ns';
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tRTW = '1.666ns';
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tCS = '1.666ns'
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