2c1052cd4d
This patch does a bunch of house-keeping updates on the DMA, including indentation, and formatting, but most importantly breaks out the response handling such that it can be shared between the atomic and timing modes. It also removes a potential bug caused by the atomic handling of responses only deleting the allocated request (pkt->req) once the DMA action completes instead of doing so for every packet. Before this patch, the handling of responses was near identical for atomic and timing, but the code was simply duplicated. With this patch, the handleResp method deals with the responses in both cases. There are further updates to make after removing the NACKs, but that will be part of a separate follow-up patch. This patch does not change the behaviour of any regression.
265 lines
8.2 KiB
C++
265 lines
8.2 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Andreas Hansson
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*/
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#include "base/chunk_generator.hh"
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#include "debug/DMA.hh"
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#include "debug/Drain.hh"
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#include "dev/dma_device.hh"
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#include "sim/system.hh"
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DmaPort::DmaPort(MemObject *dev, System *s)
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: MasterPort(dev->name() + ".dma", dev), device(dev), sys(s),
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masterId(s->getMasterId(dev->name())),
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pendingCount(0), drainEvent(NULL),
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inRetry(false)
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{ }
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void
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DmaPort::handleResp(PacketPtr pkt, Tick delay)
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{
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// should always see a response with a sender state
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assert(pkt->isResponse());
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// get the DMA sender state
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DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState);
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assert(state);
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DPRINTF(DMA, "Received response %s for addr: %#x size: %d nb: %d," \
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" tot: %d sched %d\n",
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pkt->cmdString(), pkt->getAddr(), pkt->req->getSize(),
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state->numBytes, state->totBytes,
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state->completionEvent ?
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state->completionEvent->scheduled() : 0);
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assert(pendingCount != 0);
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pendingCount--;
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// update the number of bytes received based on the request rather
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// than the packet as the latter could be rounded up to line sizes
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state->numBytes += pkt->req->getSize();
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assert(state->totBytes >= state->numBytes);
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// if we have reached the total number of bytes for this DMA
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// request, then signal the completion and delete the sate
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if (state->totBytes == state->numBytes) {
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if (state->completionEvent) {
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delay += state->delay;
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if (delay)
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device->schedule(state->completionEvent, curTick() + delay);
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else
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state->completionEvent->process();
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}
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delete state;
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}
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// delete the request that we created and also the packet
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delete pkt->req;
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delete pkt;
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// we might be drained at this point, if so signal the drain event
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if (pendingCount == 0 && drainEvent) {
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drainEvent->process();
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drainEvent = NULL;
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}
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}
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bool
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DmaPort::recvTimingResp(PacketPtr pkt)
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{
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// We shouldn't ever get a block in ownership state
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assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted()));
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handleResp(pkt);
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return true;
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}
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DmaDevice::DmaDevice(const Params *p)
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: PioDevice(p), dmaPort(this, sys)
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{ }
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void
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DmaDevice::init()
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{
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if (!dmaPort.isConnected())
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panic("DMA port of %s not connected to anything!", name());
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PioDevice::init();
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}
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unsigned int
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DmaDevice::drain(Event *de)
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{
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unsigned int count = pioPort.drain(de) + dmaPort.drain(de);
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if (count)
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changeState(Draining);
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else
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changeState(Drained);
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return count;
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}
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unsigned int
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DmaPort::drain(Event *de)
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{
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if (pendingCount == 0)
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return 0;
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drainEvent = de;
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DPRINTF(Drain, "DmaPort not drained\n");
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return 1;
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}
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void
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DmaPort::recvRetry()
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{
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assert(transmitList.size());
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bool result = true;
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do {
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PacketPtr pkt = transmitList.front();
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DPRINTF(DMA, "Retry on %s addr %#x\n",
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pkt->cmdString(), pkt->getAddr());
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result = sendTimingReq(pkt);
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if (result) {
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DPRINTF(DMA, "-- Done\n");
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transmitList.pop_front();
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inRetry = false;
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} else {
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inRetry = true;
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DPRINTF(DMA, "-- Failed, queued\n");
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}
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} while (result && transmitList.size());
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DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n",
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transmitList.size(), inRetry);
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}
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void
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DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event,
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uint8_t *data, Tick delay, Request::Flags flag)
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{
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// one DMA request sender state for every action, that is then
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// split into many requests and packets based on the block size,
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// i.e. cache line size
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DmaReqState *reqState = new DmaReqState(event, size, delay);
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DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size,
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event ? event->scheduled() : -1);
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for (ChunkGenerator gen(addr, size, peerBlockSize());
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!gen.done(); gen.next()) {
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Request *req = new Request(gen.addr(), gen.size(), flag, masterId);
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PacketPtr pkt = new Packet(req, cmd);
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// Increment the data pointer on a write
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if (data)
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pkt->dataStatic(data + gen.complete());
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pkt->senderState = reqState;
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DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(),
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gen.size());
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queueDma(pkt);
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}
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}
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void
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DmaPort::queueDma(PacketPtr pkt)
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{
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transmitList.push_back(pkt);
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// remember that we have another packet pending, this will only be
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// decremented once a response comes back
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pendingCount++;
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sendDma();
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}
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void
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DmaPort::sendDma()
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{
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// some kind of selcetion between access methods
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// more work is going to have to be done to make
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// switching actually work
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assert(transmitList.size());
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PacketPtr pkt = transmitList.front();
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Enums::MemoryMode state = sys->getMemoryMode();
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if (state == Enums::timing) {
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if (inRetry) {
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DPRINTF(DMA, "Can't send immediately, waiting for retry\n");
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return;
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}
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DPRINTF(DMA, "Attempting to send %s addr %#x\n",
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pkt->cmdString(), pkt->getAddr());
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bool result;
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do {
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result = sendTimingReq(pkt);
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if (result) {
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transmitList.pop_front();
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DPRINTF(DMA, "-- Done\n");
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} else {
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inRetry = true;
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DPRINTF(DMA, "-- Failed: queued\n");
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}
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} while (result && transmitList.size());
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} else if (state == Enums::atomic) {
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transmitList.pop_front();
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DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n",
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pkt->req->getPaddr(), pkt->req->getSize());
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Tick lat = sendAtomic(pkt);
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handleResp(pkt, lat);
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} else
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panic("Unknown memory mode.");
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}
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MasterPort &
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DmaDevice::getMasterPort(const std::string &if_name, int idx)
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{
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if (if_name == "dma") {
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return dmaPort;
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}
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return PioDevice::getMasterPort(if_name, idx);
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}
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