8149245ecc
Currently the gem5 standard library does not define a class to represent a cluster of CPUs. The SubSystem class has been extended in some python modules [1] to define clock/voltage domains shared by a group of CPUs (the cluster), and to provide some utility functions for top level configs. This patch is moving the aforementioned class within the gem5 standard library, to let other ISAs and scripts make use of it. Adding a cpu cluster class to the gem5 library will have the benefit of standardizing the interface to cpus in the toplevel configs Most of the new class still resides in the python world: we want the class to be as generic as possible and we want to make its use optional [1]: https://github.com/gem5/gem5/blob/v22.0.0.0/\ configs/example/arm/devices.py#L96 Change-Id: Idb05263a244e28bffa9eac811c6deb62ebb76a74 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65891 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
122 lines
5.1 KiB
Python
122 lines
5.1 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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DebugFlag('Activity')
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DebugFlag('Commit')
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DebugFlag('Context')
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DebugFlag('Decode')
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DebugFlag('DynInst')
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DebugFlag('ExecEnable',
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'Filter: Enable exec tracing (no tracing without this)')
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DebugFlag('ExecCPSeq', 'Format: Instruction sequence number')
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DebugFlag('ExecEffAddr', 'Format: Include effective address')
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DebugFlag('ExecFaulting', 'Trace faulting instructions')
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DebugFlag('ExecFetchSeq', 'Format: Fetch sequence number')
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DebugFlag('ExecOpClass', 'Format: Include operand class')
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DebugFlag('ExecRegDelta')
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DebugFlag('ExecResult', 'Format: Include results from execution')
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DebugFlag('ExecSymbol', 'Format: Try to include symbol names')
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DebugFlag('ExecThread', 'Format: Include thread ID in trace')
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DebugFlag('ExecMicro', 'Filter: Include microops')
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DebugFlag('ExecMacro', 'Filter: Include macroops')
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DebugFlag('ExecUser', 'Filter: Trace user mode instructions')
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DebugFlag('ExecKernel', 'Filter: Trace kernel mode instructions')
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DebugFlag('ExecAsid', 'Format: Include ASID in trace')
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DebugFlag('ExecFlags', 'Format: Include instruction flags in trace')
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DebugFlag('Fetch')
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DebugFlag('HtmCpu', 'Hardware Transactional Memory (CPU side)')
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DebugFlag('InvalidReg')
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DebugFlag('O3PipeView')
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DebugFlag('PCEvent')
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DebugFlag('Quiesce')
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DebugFlag('Mwait')
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CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
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'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
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'ExecResult', 'ExecSymbol', 'ExecThread',
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'ExecMicro', 'ExecMacro', 'ExecUser', 'ExecKernel',
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'ExecAsid', 'ExecFlags' ])
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CompoundFlag('Exec', [ 'ExecEnable', 'ExecOpClass', 'ExecThread',
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'ExecEffAddr', 'ExecResult', 'ExecSymbol', 'ExecMicro', 'ExecMacro',
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'ExecFaulting', 'ExecUser', 'ExecKernel' ])
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CompoundFlag('ExecNoTicks', [ 'Exec', 'FmtTicksOff' ])
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Source('func_unit.cc')
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Source('pc_event.cc')
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SimObject('FuncUnit.py', sim_objects=['OpDesc', 'FUDesc'], enums=['OpClass'])
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SimObject('StaticInstFlags.py', enums=['StaticInstFlags'])
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# Only build the protobuf instructions tracer if we have protobuf support.
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SimObject('InstPBTrace.py', sim_objects=['InstPBTrace'], tags='protobuf')
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Source('inst_pb_trace.cc', tags='protobuf')
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SimObject('CheckerCPU.py', sim_objects=['CheckerCPU'])
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SimObject('BaseCPU.py', sim_objects=['BaseCPU'])
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SimObject('CpuCluster.py', sim_objects=['CpuCluster'])
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SimObject('CPUTracers.py', sim_objects=[
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'ExeTracer', 'IntelTrace', 'NativeTrace'])
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SimObject('TimingExpr.py', sim_objects=[
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'TimingExpr', 'TimingExprLiteral', 'TimingExprSrcReg', 'TimingExprLet',
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'TimingExprRef', 'TimingExprUn', 'TimingExprBin', 'TimingExprIf'],
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enums=['TimingExprOp'])
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Source('activity.cc')
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Source('base.cc')
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Source('exetrace.cc')
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Source('inteltrace.cc')
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Source('nativetrace.cc')
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Source('nop_static_inst.cc')
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Source('null_static_inst.cc')
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Source('profile.cc')
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Source('reg_class.cc')
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Source('static_inst.cc')
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Source('simple_thread.cc')
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Source('thread_context.cc')
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Source('thread_state.cc')
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Source('timing_expr.cc')
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SimObject('DummyChecker.py', sim_objects=['DummyChecker'])
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Source('checker/cpu.cc')
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DebugFlag('Checker')
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