f3e3c60805
Change-Id: Ie2e2278ecdc5213db74999e3561b2918937c2c2e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2553 lines
82 KiB
C++
2553 lines
82 KiB
C++
/*
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* Copyright (c) 2011-2013,2017-2024 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/arm/insts/misc64.hh"
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#include "arch/arm/isa.hh"
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#include "arch/arm/tlbi_op.hh"
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namespace gem5
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{
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using namespace ArmISA;
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std::string
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ImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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ccprintf(ss, "#0x%x", imm);
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return ss.str();
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}
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std::string
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RegOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printIntReg(ss, op1);
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return ss.str();
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}
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std::string
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RegImmImmOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printIntReg(ss, op1);
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ccprintf(ss, "#0x%x", imm1);
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ss << ", ";
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ccprintf(ss, "#0x%x", imm2);
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return ss.str();
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}
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std::string
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RegRegImmImmOp64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printIntReg(ss, dest);
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ss << ", ";
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printIntReg(ss, op1);
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ccprintf(ss, ", #%d, #%d", imm1, imm2);
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return ss.str();
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}
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std::string
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RegRegRegImmOp64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss, "", false);
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printIntReg(ss, dest);
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ss << ", ";
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printIntReg(ss, op1);
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ss << ", ";
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printIntReg(ss, op2);
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ccprintf(ss, ", #%d", imm);
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return ss.str();
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}
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std::string
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UnknownOp64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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return csprintf("%-10s (inst %#08x)", "unknown", encoding());
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}
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uint32_t
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MiscRegOp64::_iss(const MiscRegNum64 &misc_reg, RegIndex int_index) const
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{
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return _miscRead |
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(misc_reg.crm << 1) |
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(int_index << 5) |
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(misc_reg.crn << 10) |
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(misc_reg.op1 << 14) |
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(misc_reg.op2 << 17) |
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(misc_reg.op0 << 20);
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}
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Fault
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MiscRegOp64::generateTrap(ExceptionLevel el) const
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{
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return generateTrap(el, ExceptionClass::TRAPPED_MSR_MRS_64, iss());
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}
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Fault
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MiscRegOp64::generateTrap(ExceptionLevel el, ExceptionClass ec,
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uint32_t iss) const
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{
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switch (el) {
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case EL1:
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return std::make_shared<SupervisorTrap>(getEMI(), iss, ec);
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case EL2:
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return std::make_shared<HypervisorTrap>(getEMI(), iss, ec);
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case EL3:
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return std::make_shared<SecureMonitorTrap>(getEMI(), iss, ec);
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default:
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panic("Invalid EL: %d\n", el);
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}
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}
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RegVal
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MiscRegImmOp64::miscRegImm() const
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{
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switch (dest) {
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case MISCREG_SPSEL:
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return imm & 0x1;
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case MISCREG_PAN:
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return (imm & 0x1) << 22;
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case MISCREG_UAO:
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return (imm & 0x1) << 23;
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default:
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panic("Not a valid PSTATE field register\n");
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}
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}
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std::string
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MiscRegImmOp64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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printMiscReg(ss, dest);
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ss << ", ";
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ccprintf(ss, "#0x%x", imm);
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return ss.str();
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}
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std::string
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MiscRegRegImmOp64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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printMiscReg(ss, dest);
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ss << ", ";
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printIntReg(ss, op1);
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return ss.str();
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}
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uint32_t
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MiscRegRegImmOp64::iss() const
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{
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const auto misc_reg = encodeAArch64SysReg(dest);
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assert(misc_reg.has_value());
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return _iss(misc_reg.value(), op1);
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}
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std::string
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RegMiscRegImmOp64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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printIntReg(ss, dest);
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ss << ", ";
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printMiscReg(ss, op1);
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return ss.str();
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}
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uint32_t
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RegMiscRegImmOp64::iss() const
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{
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const auto misc_reg = encodeAArch64SysReg(op1);
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assert(misc_reg.has_value());
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return _iss(misc_reg.value(), dest);
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}
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Fault
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MiscRegImplDefined64::execute(ExecContext *xc,
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trace::InstRecord *traceData) const
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{
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auto tc = xc->tcBase();
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const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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return checkFaultAccessAArch64SysReg(
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MISCREG_IMPDEF_UNIMPL, cpsr, tc, *this);
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}
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std::string
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MiscRegImplDefined64::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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return csprintf("%-10s (implementation defined)", fullMnemonic.c_str());
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}
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uint32_t
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MiscRegImplDefined64::iss() const
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{
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return _iss(miscReg, intReg);
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}
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std::string
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RegNone::generateDisassembly(
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Addr pc, const loader::SymbolTable *symtab) const
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{
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std::stringstream ss;
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printMnemonic(ss);
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printIntReg(ss, dest);
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return ss.str();
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}
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void
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TlbiOp64::tlbiAll(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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TlbiAttr attrs)
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{
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TLBIALLEL tlbi_op(regime, ss, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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void
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TlbiOp64::tlbiVmall(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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bool stage2, TlbiAttr attrs)
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{
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TLBIVMALL tlbi_op(regime, ss, stage2, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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void
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TlbiOp64::tlbiVa(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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bool last_level, TlbiAttr attrs)
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{
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if (MMU::hasUnprivRegime(regime)) {
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// The asid will only be used when e2h == 1
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bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
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auto asid = asid_16bits ? bits(value, 63, 48) :
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bits(value, 55, 48);
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TLBIMVA tlbi_op(regime, ss, static_cast<Addr>(bits(value, 43, 0)) << 12,
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asid, last_level, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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} else {
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TLBIMVAA tlbi_op(regime, ss,
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static_cast<Addr>(bits(value, 43, 0)) << 12, last_level,
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attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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}
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void
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TlbiOp64::tlbiVaa(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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bool last_level, TlbiAttr attrs)
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{
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TLBIMVAA tlbi_op(regime, ss,
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static_cast<Addr>(bits(value, 43, 0)) << 12, last_level,
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attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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void
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TlbiOp64::tlbiAsid(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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TlbiAttr attrs)
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{
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bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
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auto asid = asid_16bits ? bits(value, 63, 48) :
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bits(value, 55, 48);
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TLBIASID tlbi_op(regime, ss, asid, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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void
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TlbiOp64::tlbiIpaS2(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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bool last_level, TlbiAttr attrs)
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{
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if (EL2Enabled(tc)) {
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TLBIIPA tlbi_op(tc, TranslationRegime::EL10, ss, value,
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last_level, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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}
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void
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TlbiOp64::tlbiRvaa(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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bool last_level, TlbiAttr attrs)
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{
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TLBIRMVAA tlbi_op(regime, ss, value, last_level, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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void
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TlbiOp64::tlbiRva(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable, bool last_level,
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TlbiAttr attrs)
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{
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if (MMU::hasUnprivRegime(regime)) {
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// The asid will only be used when e2h == 1
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bool asid_16bits = ArmSystem::haveLargeAsid64(tc);
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auto asid = asid_16bits ? bits(value, 63, 48) :
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bits(value, 55, 48);
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TLBIRMVA tlbi_op(regime, ss, value, asid, last_level, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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} else {
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tlbiRvaa(tc, value, ss, regime, shareable, last_level, attrs);
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}
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}
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void
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TlbiOp64::tlbiRipaS2(ThreadContext *tc, RegVal value,
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SecurityState ss, TranslationRegime regime, bool shareable,
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bool last_level, TlbiAttr attrs)
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{
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if (EL2Enabled(tc)) {
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TLBIRIPA tlbi_op(tc, TranslationRegime::EL10, ss, value,
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last_level, attrs);
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if (shareable) {
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tlbi_op.broadcast(tc);
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} else {
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tlbi_op(tc);
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}
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}
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}
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bool
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TlbiOp64::fnxsAttrs(ThreadContext *tc)
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{
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HCRX hcrx = tc->readMiscRegNoEffect(MISCREG_HCRX_EL2);
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return currEL(tc) == EL1 &&
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HaveExt(tc, ArmExtension::FEAT_XS) &&
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HaveExt(tc, ArmExtension::FEAT_HCX) &&
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isHcrxEL2Enabled(tc) && hcrx.fnxs;
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}
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std::unordered_map<MiscRegIndex, TlbiOp64::TlbiFunc> TlbiOp64::tlbiOps = {
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{ MISCREG_TLBI_ALLE3, [](ThreadContext *tc, RegVal value)
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{
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TlbiOp64::tlbiAll(tc, value,
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SecurityState::Secure, // secure
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TranslationRegime::EL3, // regime
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false); // shareable
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}
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},
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{ MISCREG_TLBI_ALLE3NXS, [](ThreadContext *tc, RegVal value)
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{
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TlbiOp64::tlbiAll(tc, value,
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SecurityState::Secure, // secure
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TranslationRegime::EL3, // regime
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false, // shareable
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TlbiAttr::ExcludeXS); // attrs
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}
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},
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{ MISCREG_TLBI_ALLE3IS, [](ThreadContext *tc, RegVal value)
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{
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TlbiOp64::tlbiAll(tc, value,
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SecurityState::Secure, // secure
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TranslationRegime::EL3, // regime
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true); // shareable
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}
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},
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{ MISCREG_TLBI_ALLE3ISNXS, [](ThreadContext *tc, RegVal value)
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{
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TlbiOp64::tlbiAll(tc, value,
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SecurityState::Secure, // secure
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TranslationRegime::EL3, // regime
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true, // shareable
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TlbiAttr::ExcludeXS); // attrs
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}
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},
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{ MISCREG_TLBI_ALLE3OS, [](ThreadContext *tc, RegVal value)
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{
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TlbiOp64::tlbiAll(tc, value,
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SecurityState::Secure, // secure
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TranslationRegime::EL3, // regime
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true); // shareable
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}
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},
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{ MISCREG_TLBI_ALLE3OSNXS, [](ThreadContext *tc, RegVal value)
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{
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TlbiOp64::tlbiAll(tc, value,
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SecurityState::Secure, // secure
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TranslationRegime::EL3, // regime
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true, // shareable
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TlbiAttr::ExcludeXS); // attrs
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}
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},
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{ MISCREG_TLBI_ALLE2, [](ThreadContext *tc, RegVal value)
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{
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const TranslationRegime regime = ELIsInHost(tc, EL2) ?
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TranslationRegime::EL20 : TranslationRegime::EL2;
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TlbiOp64::tlbiAll(tc, value,
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securityStateAtEL(tc, EL2), // secure
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regime, // regime
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false); // shareable
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}
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},
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{ MISCREG_TLBI_ALLE2NXS, [](ThreadContext *tc, RegVal value)
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{
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const TranslationRegime regime = ELIsInHost(tc, EL2) ?
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TranslationRegime::EL20 : TranslationRegime::EL2;
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TlbiOp64::tlbiAll(tc, value,
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securityStateAtEL(tc, EL2), // secure
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regime, // regime
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false, // shareable
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TlbiAttr::ExcludeXS); // attrs
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}
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},
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{ MISCREG_TLBI_ALLE2IS, [](ThreadContext *tc, RegVal value)
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{
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const TranslationRegime regime = ELIsInHost(tc, EL2) ?
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TranslationRegime::EL20 : TranslationRegime::EL2;
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TlbiOp64::tlbiAll(tc, value,
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securityStateAtEL(tc, EL2), // secure
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regime, // regime
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true); // shareable
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}
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},
|
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|
{ MISCREG_TLBI_ALLE2ISNXS, [](ThreadContext *tc, RegVal value)
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|
{
|
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const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
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|
|
TlbiOp64::tlbiAll(tc, value,
|
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securityStateAtEL(tc, EL2), // secure
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regime, // regime
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true, // shareable
|
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TlbiAttr::ExcludeXS); // attrs
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}
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},
|
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|
|
{ MISCREG_TLBI_ALLE2OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true); // shareable
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE2OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false); // shareable
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true); // shareable
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true); // shareable
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ALLE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiAll(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VMALLE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // stage2
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // stage2
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // stage2
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // stage2
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // stage2
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // stage2
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLS12E1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
true); // stage2
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLS12E1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
true, // stage2
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLS12E1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true); // stage2
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLS12E1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true, // stage2
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLS12E1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true); // stage2
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VMALLS12E1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVmall(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true, // stage2
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VAE3, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE3NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VAE3IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE3ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE3OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE3OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VALE3, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE3NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VALE3IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE3ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VALE3OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE3OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
SecurityState::Secure, // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE2, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE2NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE2IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
TranslationRegime::EL2, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE2ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
TranslationRegime::EL2, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VAE2OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc,EL2), // secure
|
|
TranslationRegime::EL2, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE2OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc,EL2), // secure
|
|
TranslationRegime::EL2, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_VALE2, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE2NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE2IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE2ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE2OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE2OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VALE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ASIDE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiAsid(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ASIDE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiAsid(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ASIDE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiAsid(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ASIDE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiAsid(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ASIDE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiAsid(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_ASIDE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiAsid(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAAE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAAE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAAE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAAE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAAE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAAE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAALE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAALE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAALE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAALE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAALE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_VAALE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiVaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2E1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
false); // last level
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2E1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
false, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2E1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false); // last level
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2E1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_IPAS2E1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false); // last level
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2E1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2LE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
true); // last level
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2LE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
true, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_IPAS2LE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true); // last level
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2LE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_IPAS2LE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true); // last level
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_IPAS2LE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiIpaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true, // last level
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_RVAE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAAE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAAE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAAE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAAE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_RVAAE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAAE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAALE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAALE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
// Check for Force Broadcast. Ignored if HCR_EL2.TGE == 1
|
|
HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
|
|
bool shareable = currEL(tc) == EL1 && EL2Enabled(tc) &&
|
|
hcr.fb && !hcr.tge;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
shareable, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAALE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAALE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAALE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
const TlbiAttr attrs = fnxsAttrs(tc) ?
|
|
TlbiAttr::ExcludeXS : TlbiAttr::None;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
attrs); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAALE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL0) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL10;
|
|
|
|
TlbiOp64::tlbiRvaa(tc, value,
|
|
securityStateAtEL(tc, translationEl(regime)), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2E1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2LE1, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2LE1NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
false, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2LE1IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2LE1ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2LE1OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RIPAS2LE1OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
tlbiRipaS2(tc, value,
|
|
securityStateAtEL(tc, EL1), // secure
|
|
TranslationRegime::EL10, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE2, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE2NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE2IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE2ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE2OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE2OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE2, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE2NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
false, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE2IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE2ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE2OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE2OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
const TranslationRegime regime = ELIsInHost(tc, EL2) ?
|
|
TranslationRegime::EL20 : TranslationRegime::EL2;
|
|
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL2), // secure
|
|
regime, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE3, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE3NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE3IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE3ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE3OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVAE3OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
false, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE3, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE3NXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
false, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE3IS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE3ISNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE3OS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true); // last level only
|
|
}
|
|
},
|
|
|
|
{ MISCREG_TLBI_RVALE3OSNXS, [](ThreadContext *tc, RegVal value)
|
|
{
|
|
TlbiOp64::tlbiRva(tc, value,
|
|
securityStateAtEL(tc, EL3), // secure
|
|
TranslationRegime::EL3, // regime
|
|
true, // shareable
|
|
true, // last level only
|
|
TlbiAttr::ExcludeXS); // attrs
|
|
}
|
|
},
|
|
};
|
|
|
|
void
|
|
TlbiOp64::performTlbi(ExecContext *xc, MiscRegIndex dest_idx, RegVal value) const
|
|
{
|
|
ThreadContext* tc = xc->tcBase();
|
|
|
|
if (auto it = tlbiOps.find(dest_idx); it != tlbiOps.end()) {
|
|
it->second(tc, value);
|
|
} else {
|
|
panic("Invalid TLBI\n");
|
|
}
|
|
}
|
|
|
|
} // namespace gem5
|