a8a2ab5ec6
It is no longer necessary anywhere in gem5. Change-Id: Iac999acf8c59ee7387214057bebb617acd01617c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/62197 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com>
269 lines
8.8 KiB
C++
269 lines
8.8 KiB
C++
/*
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* Copyright (c) 2011-2012, 2016-2018, 2020 ARM Limited
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_THREAD_CONTEXT_HH__
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#define __CPU_THREAD_CONTEXT_HH__
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#include <iostream>
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#include <string>
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#include "arch/generic/htm.hh"
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#include "arch/generic/isa.hh"
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#include "arch/generic/pcstate.hh"
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#include "base/types.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/reg_class.hh"
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namespace gem5
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{
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// DTB pointers.
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class BaseCPU;
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class BaseMMU;
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class BaseTLB;
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class CheckerCPU;
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class Checkpoint;
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class InstDecoder;
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class PortProxy;
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class Process;
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class System;
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class Packet;
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using PacketPtr = Packet *;
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/**
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* ThreadContext is the external interface to all thread state for
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* anything outside of the CPU. It provides all accessor methods to
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* state that might be needed by external objects, ranging from
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* register values to things such as kernel stats. It is an abstract
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* base class; the CPU can create its own ThreadContext by
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* deriving from it.
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*
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* The ThreadContext is slightly different than the ExecContext. The
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* ThreadContext provides access to an individual thread's state; an
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* ExecContext provides ISA access to the CPU (meaning it is
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* implicitly multithreaded on SMT systems). Additionally the
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* ThreadState is an abstract class that exactly defines the
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* interface; the ExecContext is a more implicit interface that must
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* be implemented so that the ISA can access whatever state it needs.
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*/
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class ThreadContext : public PCEventScope
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{
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protected:
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bool useForClone = false;
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public:
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bool getUseForClone() { return useForClone; }
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void setUseForClone(bool new_val) { useForClone = new_val; }
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enum Status
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{
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/// Running. Instructions should be executed only when
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/// the context is in this state.
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Active,
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/// Temporarily inactive. Entered while waiting for
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/// synchronization, etc.
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Suspended,
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/// Trying to exit and waiting for an event to completely exit.
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/// Entered when target executes an exit syscall.
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Halting,
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/// Permanently shut down. Entered when target executes
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/// m5exit pseudo-instruction. When all contexts enter
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/// this state, the simulation will terminate.
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Halted
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};
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virtual ~ThreadContext() { };
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virtual BaseCPU *getCpuPtr() = 0;
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virtual int cpuId() const = 0;
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virtual uint32_t socketId() const = 0;
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virtual int threadId() const = 0;
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virtual void setThreadId(int id) = 0;
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virtual ContextID contextId() const = 0;
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virtual void setContextId(ContextID id) = 0;
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virtual BaseMMU *getMMUPtr() = 0;
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virtual CheckerCPU *getCheckerCpuPtr() = 0;
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virtual BaseISA *getIsaPtr() const = 0;
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virtual InstDecoder *getDecoderPtr() = 0;
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virtual System *getSystemPtr() = 0;
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virtual void sendFunctional(PacketPtr pkt);
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virtual Process *getProcessPtr() = 0;
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virtual void setProcessPtr(Process *p) = 0;
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virtual Status status() const = 0;
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virtual void setStatus(Status new_status) = 0;
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/// Set the status to Active.
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virtual void activate() = 0;
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/// Set the status to Suspended.
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virtual void suspend() = 0;
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/// Set the status to Halted.
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virtual void halt() = 0;
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/// Quiesce thread context
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void quiesce();
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/// Quiesce, suspend, and schedule activate at resume
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void quiesceTick(Tick resume);
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virtual void takeOverFrom(ThreadContext *old_context) = 0;
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virtual void regStats(const std::string &name) {};
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virtual void scheduleInstCountEvent(Event *event, Tick count) = 0;
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virtual void descheduleInstCountEvent(Event *event) = 0;
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virtual Tick getCurrentInstCount() = 0;
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// Not necessarily the best location for these...
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// Having an extra function just to read these is obnoxious
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virtual Tick readLastActivate() = 0;
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virtual Tick readLastSuspend() = 0;
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virtual void copyArchRegs(ThreadContext *tc) = 0;
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virtual void clearArchRegs() = 0;
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//
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// New accessors for new decoder.
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//
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virtual RegVal getReg(const RegId ®) const;
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virtual void getReg(const RegId ®, void *val) const = 0;
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virtual void *getWritableReg(const RegId ®) = 0;
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virtual void setReg(const RegId ®, RegVal val);
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virtual void setReg(const RegId ®, const void *val) = 0;
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virtual const PCStateBase &pcState() const = 0;
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virtual void pcState(const PCStateBase &val) = 0;
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void
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pcState(Addr addr)
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{
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std::unique_ptr<PCStateBase> new_pc(getIsaPtr()->newPCState(addr));
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pcState(*new_pc);
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}
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virtual void pcStateNoRecord(const PCStateBase &val) = 0;
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virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
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virtual RegVal readMiscReg(RegIndex misc_reg) = 0;
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virtual void setMiscRegNoEffect(RegIndex misc_reg, RegVal val) = 0;
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virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0;
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// Also not necessarily the best location for these two. Hopefully will go
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// away once we decide upon where st cond failures goes.
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virtual unsigned readStCondFailures() const = 0;
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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// This function exits the thread context in the CPU and returns
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// 1 if the CPU has no more active threads (meaning it's OK to exit);
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// Used in syscall-emulation mode when a thread calls the exit syscall.
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virtual int exit() { return 1; };
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/** function to compare two thread contexts (for debugging) */
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static void compare(ThreadContext *one, ThreadContext *two);
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// hardware transactional memory
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virtual void htmAbortTransaction(uint64_t htm_uid,
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HtmFailureFaultCause cause) = 0;
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virtual BaseHTMCheckpointPtr& getHtmCheckpointPtr() = 0;
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virtual void setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) = 0;
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};
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/** @{ */
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/**
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* Thread context serialization helpers
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*
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* These helper functions provide a way to the data in a
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* ThreadContext. They are provided as separate helper function since
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* implementing them as members of the ThreadContext interface would
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* be confusing when the ThreadContext is exported via a proxy.
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*/
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void serialize(const ThreadContext &tc, CheckpointOut &cp);
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void unserialize(ThreadContext &tc, CheckpointIn &cp);
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/** @} */
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/**
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* Copy state between thread contexts in preparation for CPU handover.
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*
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* @note This method modifies the old thread contexts as well as the
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* new thread context. The old thread context will have its quiesce
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* event descheduled if it is scheduled and its status set to halted.
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*
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* @param new_tc Destination ThreadContext.
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* @param old_tc Source ThreadContext.
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*/
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void takeOverFrom(ThreadContext &new_tc, ThreadContext &old_tc);
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} // namespace gem5
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#endif
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