952c4f5eea
Change-Id: I3576df2b7bee1289db60bb6072bd9c90038ca8ce Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
86 lines
3.2 KiB
C++
86 lines
3.2 KiB
C++
/*
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* Copyright (c) 2023 Arm Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006-2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/nativetrace.hh"
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#include "base/socket.hh"
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#include "cpu/static_inst.hh"
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#include "debug/GDBMisc.hh"
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#include "params/NativeTrace.hh"
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namespace gem5
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{
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namespace trace {
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NativeTrace::NativeTrace(const Params &p)
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: ExeTracer(p), native_listener(listenSocketInetConfig(8000).build(p.name))
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{
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if (ListenSocket::allDisabled())
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fatal("All listeners are disabled!");
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native_listener->listen();
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fd = native_listener->accept();
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}
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NativeTraceRecord::NativeTraceRecord(
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NativeTrace *_parent,
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Tick _when, ThreadContext *_thread,
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const StaticInstPtr _staticInst, const PCStateBase &_pc,
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const StaticInstPtr _macroStaticInst)
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: ExeTracerRecord(_when, _thread, _staticInst, _pc,
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*_parent, _macroStaticInst),
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parent(_parent)
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{
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}
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void
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NativeTraceRecord::dump()
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{
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//Don't print what happens for each micro-op, just print out
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//once at the last op, and for regular instructions.
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if (!staticInst->isMicroop() || staticInst->isLastMicroop())
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parent->check(this);
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}
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} // namespace trace
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} // namespace gem5
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