Gabe Black 6b87ee1e1f python: Replace the Master/Slave Ports with Request/Response ports. ...

These are a little more descriptive and a little less potentially
offensive.

Change-Id: I84c30f783f0a4c242cb4f54ab272b6fdf1e9eec7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

2019-04-27 20:26:31 +00:00

..

arch

arch-arm: updateMiscReg not setting isHyp in aarch64

2019-04-26 16:13:04 +00:00

base

dev-arm: Correct cast of template parameter

2019-04-01 15:55:58 +00:00

cpu

cpu,mem: missing override specifier

2019-04-24 13:43:23 +00:00

dev

dev-arm: Move GICv3 (Re)Ditributor address in Realview.py

2019-04-25 12:48:41 +00:00

doc

sim-se: add a faux-filesystem

2019-04-25 18:11:34 +00:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

gpu-compute

arch, cpu, dev, gpu, mem, sim, python: start using getPort.

2019-03-19 10:22:50 +00:00

kern

sim-se: add a faux-filesystem

2019-04-25 18:11:34 +00:00

learning_gem5

learning_gem5: Fix vector port panic in SimpleCache

2019-04-08 22:51:38 +00:00

mem

cpu,mem: missing override specifier

2019-04-24 13:43:23 +00:00

proto

cpu: Stop extracting inst_flags from the machInst.

2018-03-27 10:57:36 +00:00

python

python: Replace the Master/Slave Ports with Request/Response ports.

2019-04-27 20:26:31 +00:00

sim

sim-se: add a faux-filesystem

2019-04-25 18:11:34 +00:00

systemc

systemc: Use the new TLM socket types in the TLM bridge SimObjects.

2019-04-24 11:00:56 +00:00

unittest

python: Replace dict.has_key with 'key in dict'

2019-02-12 17:36:12 +00:00

Doxyfile

misc: Fix BaseCPU doxygen

2018-07-10 16:41:40 +00:00

SConscript

scons: fix disable_partial logic for fast binary

2019-03-18 22:22:25 +00:00