ad44834907
1. Make sure connectMemPorts() only gets called when the CPU's peer gets changed. This is done by making setPeer() virtual, and overriding it in the CPU's ports. When it gets called on a CPU's port (dcache specifically), it calls the normal setPeer() function, and also connectMemPorts().
2. Consolidate redundant code that handles switching in a CPU.
src/cpu/base.cc:
Move common code of switching over peers to base CPU.
src/cpu/base.hh:
Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
Add in function that updates thread context's ports.
Also use updated function to takeOverFrom() in BaseCPU. This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
Add function to dcache port that will update the memory ports upon getting a new peer.
Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Add function that will update thread context's memory ports upon getting a new peer.
Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
Make setPeer virtual so that other classes can override it.
--HG--
extra : convert_revision : 2050f1241dd2e83875d281cfc5ad5c6c8705fdaf
463 lines
12 KiB
C++
463 lines
12 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Nathan Binkert
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*/
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#include <iostream>
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#include <string>
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#include <sstream>
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#include "base/cprintf.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "cpu/base.hh"
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#include "cpu/cpuevent.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/profile.hh"
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#include "sim/sim_exit.hh"
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#include "sim/param.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/system.hh"
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#include "base/trace.hh"
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// Hack
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#include "sim/stat_control.hh"
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using namespace std;
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vector<BaseCPU *> BaseCPU::cpuList;
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// This variable reflects the max number of threads in any CPU. Be
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// careful to only use it once all the CPUs that you care about have
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// been initialized
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int maxThreadsPerCPU = 1;
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CPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival,
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BaseCPU *_cpu)
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: Event(q, Event::Progress_Event_Pri), interval(ival),
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lastNumInst(0), cpu(_cpu)
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{
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if (interval)
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schedule(curTick + interval);
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}
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void
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CPUProgressEvent::process()
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{
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Counter temp = cpu->totalInstructions();
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#ifndef NDEBUG
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double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1));
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DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n",
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cpu->name(), temp - lastNumInst, ipc);
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ipc = 0.0;
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#else
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cprintf("%lli: %s progress event, instructions committed: %lli\n",
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curTick, cpu->name(), temp - lastNumInst);
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#endif
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lastNumInst = temp;
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schedule(curTick + interval);
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}
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const char *
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CPUProgressEvent::description()
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{
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return "CPU Progress event";
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}
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#if FULL_SYSTEM
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BaseCPU::BaseCPU(Params *p)
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: MemObject(p->name), clock(p->clock), instCnt(0),
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params(p), number_of_threads(p->numberOfThreads), system(p->system),
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phase(p->phase)
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#else
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BaseCPU::BaseCPU(Params *p)
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: MemObject(p->name), clock(p->clock), params(p),
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number_of_threads(p->numberOfThreads), system(p->system),
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phase(p->phase)
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#endif
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{
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// currentTick = curTick;
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DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
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// add self to global list of CPUs
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cpuList.push_back(this);
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DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
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this);
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if (number_of_threads > maxThreadsPerCPU)
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maxThreadsPerCPU = number_of_threads;
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// allocate per-thread instruction-based event queues
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comInstEventQueue = new EventQueue *[number_of_threads];
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for (int i = 0; i < number_of_threads; ++i)
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comInstEventQueue[i] = new EventQueue("instruction-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_insts_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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schedExitSimLoop("a thread reached the max instruction count",
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p->max_insts_any_thread, 0,
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comInstEventQueue[i]);
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if (p->max_insts_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = number_of_threads;
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comInstEventQueue[i],
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"all threads reached the max instruction count",
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p->max_insts_all_threads, *counter);
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}
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// allocate per-thread load-based event queues
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comLoadEventQueue = new EventQueue *[number_of_threads];
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for (int i = 0; i < number_of_threads; ++i)
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comLoadEventQueue[i] = new EventQueue("load-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (p->max_loads_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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schedExitSimLoop("a thread reached the max load count",
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p->max_loads_any_thread, 0,
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comLoadEventQueue[i]);
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if (p->max_loads_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = number_of_threads;
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comLoadEventQueue[i],
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"all threads reached the max load count",
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p->max_loads_all_threads, *counter);
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}
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functionTracingEnabled = false;
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if (p->functionTrace) {
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functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
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currentFunctionStart = currentFunctionEnd = 0;
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functionEntryTick = p->functionTraceStart;
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if (p->functionTraceStart == 0) {
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functionTracingEnabled = true;
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} else {
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Event *e =
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new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
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true);
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e->schedule(p->functionTraceStart);
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}
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}
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#if FULL_SYSTEM
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profileEvent = NULL;
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if (params->profile)
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profileEvent = new ProfileEvent(this, params->profile);
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#endif
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}
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BaseCPU::Params::Params()
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{
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#if FULL_SYSTEM
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profile = false;
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#endif
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checker = NULL;
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}
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void
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BaseCPU::enableFunctionTrace()
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{
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functionTracingEnabled = true;
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}
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BaseCPU::~BaseCPU()
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{
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}
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void
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BaseCPU::init()
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{
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if (!params->deferRegistration)
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registerThreadContexts();
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}
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void
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BaseCPU::startup()
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{
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#if FULL_SYSTEM
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if (!params->deferRegistration && profileEvent)
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profileEvent->schedule(curTick);
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#endif
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if (params->progress_interval) {
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new CPUProgressEvent(&mainEventQueue, params->progress_interval,
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this);
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}
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}
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void
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BaseCPU::regStats()
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{
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using namespace Stats;
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numCycles
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.name(name() + ".numCycles")
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.desc("number of cpu cycles simulated")
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;
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int size = threadContexts.size();
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if (size > 1) {
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for (int i = 0; i < size; ++i) {
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stringstream namestr;
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ccprintf(namestr, "%s.ctx%d", name(), i);
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threadContexts[i]->regStats(namestr.str());
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}
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} else if (size == 1)
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threadContexts[0]->regStats(name());
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#if FULL_SYSTEM
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#endif
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}
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Tick
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BaseCPU::nextCycle()
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{
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Tick next_tick = curTick - phase + clock - 1;
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next_tick -= (next_tick % clock);
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next_tick += phase;
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return next_tick;
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}
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Tick
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BaseCPU::nextCycle(Tick begin_tick)
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{
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Tick next_tick = begin_tick;
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next_tick -= (next_tick % clock);
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next_tick += phase;
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while (next_tick < curTick)
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next_tick += clock;
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assert(next_tick >= curTick);
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return next_tick;
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}
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void
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BaseCPU::registerThreadContexts()
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{
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *tc = threadContexts[i];
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#if FULL_SYSTEM
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int id = params->cpu_id;
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if (id != -1)
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id += i;
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tc->setCpuId(system->registerThreadContext(tc, id));
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#else
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tc->setCpuId(tc->getProcessPtr()->registerThreadContext(tc));
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#endif
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}
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}
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int
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BaseCPU::findContext(ThreadContext *tc)
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{
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for (int i = 0; i < threadContexts.size(); ++i) {
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if (tc == threadContexts[i])
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return i;
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}
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return 0;
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}
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void
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BaseCPU::switchOut()
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{
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// panic("This CPU doesn't support sampling!");
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#if FULL_SYSTEM
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if (profileEvent && profileEvent->scheduled())
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profileEvent->deschedule();
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#endif
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}
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void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
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{
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assert(threadContexts.size() == oldCPU->threadContexts.size());
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for (int i = 0; i < threadContexts.size(); ++i) {
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ThreadContext *newTC = threadContexts[i];
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ThreadContext *oldTC = oldCPU->threadContexts[i];
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newTC->takeOverFrom(oldTC);
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CpuEvent::replaceThreadContext(oldTC, newTC);
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assert(newTC->readCpuId() == oldTC->readCpuId());
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#if FULL_SYSTEM
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system->replaceThreadContext(newTC, newTC->readCpuId());
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#else
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assert(newTC->getProcessPtr() == oldTC->getProcessPtr());
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newTC->getProcessPtr()->replaceThreadContext(newTC, newTC->readCpuId());
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#endif
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// TheISA::compareXCs(oldXC, newXC);
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}
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#if FULL_SYSTEM
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interrupts = oldCPU->interrupts;
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for (int i = 0; i < threadContexts.size(); ++i)
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threadContexts[i]->profileClear();
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// The Sampler must take care of this!
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// if (profileEvent)
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// profileEvent->schedule(curTick);
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#endif
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// Connect new CPU to old CPU's memory only if new CPU isn't
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// connected to anything. Also connect old CPU's memory to new
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// CPU.
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Port *peer;
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if (ic->getPeer() == NULL) {
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peer = oldCPU->getPort("icache_port")->getPeer();
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ic->setPeer(peer);
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} else {
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peer = ic->getPeer();
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}
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peer->setPeer(ic);
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if (dc->getPeer() == NULL) {
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peer = oldCPU->getPort("dcache_port")->getPeer();
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dc->setPeer(peer);
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} else {
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peer = dc->getPeer();
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}
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peer->setPeer(dc);
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}
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#if FULL_SYSTEM
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BaseCPU::ProfileEvent::ProfileEvent(BaseCPU *_cpu, int _interval)
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: Event(&mainEventQueue), cpu(_cpu), interval(_interval)
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{ }
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void
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BaseCPU::ProfileEvent::process()
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{
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for (int i = 0, size = cpu->threadContexts.size(); i < size; ++i) {
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ThreadContext *tc = cpu->threadContexts[i];
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tc->profileSample();
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}
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schedule(curTick + interval);
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}
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void
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BaseCPU::post_interrupt(int int_num, int index)
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{
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interrupts.post(int_num, index);
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}
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void
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BaseCPU::clear_interrupt(int int_num, int index)
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{
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interrupts.clear(int_num, index);
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}
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void
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BaseCPU::clear_interrupts()
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{
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interrupts.clear_all();
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}
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uint64_t
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BaseCPU::get_interrupts(int int_num)
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{
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return interrupts.get_vec(int_num);
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}
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void
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BaseCPU::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(instCnt);
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interrupts.serialize(os);
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}
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void
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BaseCPU::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(instCnt);
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interrupts.unserialize(cp, section);
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}
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#endif // FULL_SYSTEM
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void
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BaseCPU::traceFunctionsInternal(Addr pc)
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{
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if (!debugSymbolTable)
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return;
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// if pc enters different function, print new function symbol and
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// update saved range. Otherwise do nothing.
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if (pc < currentFunctionStart || pc >= currentFunctionEnd) {
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string sym_str;
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bool found = debugSymbolTable->findNearestSymbol(pc, sym_str,
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currentFunctionStart,
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currentFunctionEnd);
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if (!found) {
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// no symbol found: use addr as label
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sym_str = csprintf("0x%x", pc);
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currentFunctionStart = pc;
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currentFunctionEnd = pc + 1;
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}
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ccprintf(*functionTraceStream, " (%d)\n%d: %s",
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curTick - functionEntryTick, curTick, sym_str);
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functionEntryTick = curTick;
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}
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}
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DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
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