1191 lines
43 KiB
C++
1191 lines
43 KiB
C++
/*
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* Copyright (c) 2019-2021 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* Copyright (c) 2013 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "mem/ruby/system/Sequencer.hh"
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#include "arch/x86/ldstflags.hh"
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#include "base/compiler.hh"
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#include "base/logging.hh"
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#include "base/str.hh"
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "debug/LLSC.hh"
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#include "debug/MemoryAccess.hh"
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#include "debug/ProtocolTrace.hh"
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#include "debug/RubyHitMiss.hh"
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#include "debug/RubySequencer.hh"
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#include "debug/RubyStats.hh"
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#include "mem/packet.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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#include "mem/ruby/protocol/PrefetchBit.hh"
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#include "mem/ruby/protocol/RubyAccessMode.hh"
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#include "mem/ruby/slicc_interface/RubyRequest.hh"
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#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"
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#include "mem/ruby/system/RubySystem.hh"
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#include "sim/system.hh"
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namespace gem5
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{
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namespace ruby
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{
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Sequencer::Sequencer(const Params &p)
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: RubyPort(p), m_IncompleteTimes(MachineType_NUM),
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deadlockCheckEvent([this]{ wakeup(); }, "Sequencer deadlock check")
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{
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m_outstanding_count = 0;
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m_dataCache_ptr = p.dcache;
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m_max_outstanding_requests = p.max_outstanding_requests;
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m_deadlock_threshold = p.deadlock_threshold;
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m_coreId = p.coreid; // for tracking the two CorePair sequencers
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assert(m_max_outstanding_requests > 0);
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assert(m_deadlock_threshold > 0);
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m_unaddressedTransactionCnt = 0;
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m_runningGarnetStandalone = p.garnet_standalone;
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m_num_pending_invs = 0;
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m_cache_inv_pkt = nullptr;
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// These statistical variables are not for display.
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// The profiler will collate these across different
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// sequencers and display those collated statistics.
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m_outstandReqHist.init(10);
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m_latencyHist.init(10);
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m_hitLatencyHist.init(10);
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m_missLatencyHist.init(10);
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for (int i = 0; i < RubyRequestType_NUM; i++) {
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m_typeLatencyHist.push_back(new statistics::Histogram());
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m_typeLatencyHist[i]->init(10);
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m_hitTypeLatencyHist.push_back(new statistics::Histogram());
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m_hitTypeLatencyHist[i]->init(10);
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m_missTypeLatencyHist.push_back(new statistics::Histogram());
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m_missTypeLatencyHist[i]->init(10);
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}
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for (int i = 0; i < MachineType_NUM; i++) {
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m_hitMachLatencyHist.push_back(new statistics::Histogram());
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m_hitMachLatencyHist[i]->init(10);
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m_missMachLatencyHist.push_back(new statistics::Histogram());
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m_missMachLatencyHist[i]->init(10);
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m_IssueToInitialDelayHist.push_back(new statistics::Histogram());
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m_IssueToInitialDelayHist[i]->init(10);
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m_InitialToForwardDelayHist.push_back(new statistics::Histogram());
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m_InitialToForwardDelayHist[i]->init(10);
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m_ForwardToFirstResponseDelayHist.push_back(
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new statistics::Histogram());
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m_ForwardToFirstResponseDelayHist[i]->init(10);
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m_FirstResponseToCompletionDelayHist.push_back(
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new statistics::Histogram());
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m_FirstResponseToCompletionDelayHist[i]->init(10);
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}
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for (int i = 0; i < RubyRequestType_NUM; i++) {
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m_hitTypeMachLatencyHist.push_back(
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std::vector<statistics::Histogram *>());
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m_missTypeMachLatencyHist.push_back(
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std::vector<statistics::Histogram *>());
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for (int j = 0; j < MachineType_NUM; j++) {
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m_hitTypeMachLatencyHist[i].push_back(new statistics::Histogram());
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m_hitTypeMachLatencyHist[i][j]->init(10);
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m_missTypeMachLatencyHist[i].push_back(
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new statistics::Histogram());
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m_missTypeMachLatencyHist[i][j]->init(10);
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}
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}
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}
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Sequencer::~Sequencer()
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{
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}
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void
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Sequencer::llscLoadLinked(const Addr claddr)
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{
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fatal_if(m_dataCache_ptr == NULL,
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"%s must have a dcache object to support LLSC requests.", name());
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AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
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if (line) {
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line->setLocked(m_version);
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DPRINTF(LLSC, "LLSC Monitor - inserting load linked - "
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"addr=0x%lx - cpu=%u\n", claddr, m_version);
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}
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}
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void
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Sequencer::llscClearMonitor(const Addr claddr)
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{
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// clear monitor is called for all stores and evictions
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if (m_dataCache_ptr == NULL)
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return;
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AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
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if (line && line->isLocked(m_version)) {
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line->clearLocked();
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DPRINTF(LLSC, "LLSC Monitor - clearing due to store - "
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"addr=0x%lx - cpu=%u\n", claddr, m_version);
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}
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}
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bool
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Sequencer::llscStoreConditional(const Addr claddr)
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{
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fatal_if(m_dataCache_ptr == NULL,
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"%s must have a dcache object to support LLSC requests.", name());
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AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
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if (!line)
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return false;
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DPRINTF(LLSC, "LLSC Monitor - clearing due to "
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"store conditional - "
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"addr=0x%lx - cpu=%u\n",
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claddr, m_version);
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if (line->isLocked(m_version)) {
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line->clearLocked();
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return true;
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} else {
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line->clearLocked();
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return false;
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}
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}
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bool
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Sequencer::llscCheckMonitor(const Addr address)
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{
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assert(m_dataCache_ptr != NULL);
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const Addr claddr = makeLineAddress(address);
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AbstractCacheEntry *line = m_dataCache_ptr->lookup(claddr);
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if (!line)
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return false;
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if (line->isLocked(m_version)) {
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return true;
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} else {
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return false;
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}
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}
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void
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Sequencer::llscClearLocalMonitor()
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{
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m_dataCache_ptr->clearLockedAll(m_version);
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}
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void
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Sequencer::wakeup()
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{
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assert(drainState() != DrainState::Draining);
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// Check for deadlock of any of the requests
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Cycles current_time = curCycle();
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// Check across all outstanding requests
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[[maybe_unused]] int total_outstanding = 0;
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for (const auto &table_entry : m_RequestTable) {
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for (const auto &seq_req : table_entry.second) {
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if (current_time - seq_req.issue_time < m_deadlock_threshold)
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continue;
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panic("Possible Deadlock detected. Aborting!\n version: %d "
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"request.paddr: 0x%x m_readRequestTable: %d current time: "
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"%u issue_time: %d difference: %d\n", m_version,
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seq_req.pkt->getAddr(), table_entry.second.size(),
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current_time * clockPeriod(), seq_req.issue_time
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* clockPeriod(), (current_time * clockPeriod())
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- (seq_req.issue_time * clockPeriod()));
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}
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total_outstanding += table_entry.second.size();
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}
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assert(m_outstanding_count == total_outstanding);
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if (m_outstanding_count > 0) {
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// If there are still outstanding requests, keep checking
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schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
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}
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}
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int
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Sequencer::functionalWrite(Packet *func_pkt)
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{
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int num_written = RubyPort::functionalWrite(func_pkt);
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for (const auto &table_entry : m_RequestTable) {
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for (const auto& seq_req : table_entry.second) {
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if (seq_req.functionalWrite(func_pkt))
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++num_written;
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}
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}
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return num_written;
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}
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void Sequencer::resetStats()
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{
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m_outstandReqHist.reset();
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m_latencyHist.reset();
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m_hitLatencyHist.reset();
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m_missLatencyHist.reset();
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for (int i = 0; i < RubyRequestType_NUM; i++) {
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m_typeLatencyHist[i]->reset();
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m_hitTypeLatencyHist[i]->reset();
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m_missTypeLatencyHist[i]->reset();
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for (int j = 0; j < MachineType_NUM; j++) {
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m_hitTypeMachLatencyHist[i][j]->reset();
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m_missTypeMachLatencyHist[i][j]->reset();
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}
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}
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for (int i = 0; i < MachineType_NUM; i++) {
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m_missMachLatencyHist[i]->reset();
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m_hitMachLatencyHist[i]->reset();
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m_IssueToInitialDelayHist[i]->reset();
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m_InitialToForwardDelayHist[i]->reset();
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m_ForwardToFirstResponseDelayHist[i]->reset();
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m_FirstResponseToCompletionDelayHist[i]->reset();
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m_IncompleteTimes[i] = 0;
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}
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}
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// Insert the request in the request table. Return RequestStatus_Aliased
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// if the entry was already present.
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RequestStatus
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Sequencer::insertRequest(PacketPtr pkt, RubyRequestType primary_type,
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RubyRequestType secondary_type)
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{
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// See if we should schedule a deadlock check
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if (!deadlockCheckEvent.scheduled() &&
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drainState() != DrainState::Draining) {
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schedule(deadlockCheckEvent, clockEdge(m_deadlock_threshold));
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}
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if (isTlbiCmdRequest(primary_type)) {
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assert(primary_type == secondary_type);
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switch (primary_type) {
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case RubyRequestType_TLBI_EXT_SYNC_COMP:
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// Don't have to store any data on this
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break;
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case RubyRequestType_TLBI:
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case RubyRequestType_TLBI_SYNC:
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{
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incrementUnaddressedTransactionCnt();
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// returns pair<inserted element, was inserted>
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[[maybe_unused]] auto insert_data = \
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m_UnaddressedRequestTable.emplace(
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getCurrentUnaddressedTransactionID(),
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SequencerRequest(
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pkt, primary_type, secondary_type, curCycle()));
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// if insert_data.second is false, wasn't inserted
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assert(insert_data.second &&
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"Another TLBI request with the same ID exists");
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DPRINTF(RubySequencer, "Inserting TLBI request %016x\n",
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getCurrentUnaddressedTransactionID());
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break;
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}
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default:
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panic("Unexpected TLBI RubyRequestType");
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}
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return RequestStatus_Ready;
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}
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// If command is MemSyncReq, it is used to invalidate the cache.
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// As the cache invalidation requests are already issued in invL1(),
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// there is no need to create a new request for the same here.
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// Instead, return RequestStatus_Aliased, and make the sequencer skip
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// an extra issueRequest
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if (pkt->cmd == MemCmd::MemSyncReq) {
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return RequestStatus_Aliased;
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}
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Addr line_addr = makeLineAddress(pkt->getAddr());
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// Check if there is any outstanding request for the same cache line.
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auto &seq_req_list = m_RequestTable[line_addr];
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// Create a default entry
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seq_req_list.emplace_back(pkt, primary_type,
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secondary_type, curCycle());
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m_outstanding_count++;
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if (seq_req_list.size() > 1) {
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return RequestStatus_Aliased;
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}
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m_outstandReqHist.sample(m_outstanding_count);
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return RequestStatus_Ready;
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}
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void
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Sequencer::markRemoved()
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{
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m_outstanding_count--;
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}
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void
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Sequencer::recordMissLatency(SequencerRequest* srequest, bool llscSuccess,
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const MachineType respondingMach,
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bool isExternalHit, Cycles initialRequestTime,
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Cycles forwardRequestTime,
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Cycles firstResponseTime)
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{
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RubyRequestType type = srequest->m_type;
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Cycles issued_time = srequest->issue_time;
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Cycles completion_time = curCycle();
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assert(curCycle() >= issued_time);
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Cycles total_lat = completion_time - issued_time;
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if ((initialRequestTime != 0) && (initialRequestTime < issued_time)) {
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// if the request was combined in the protocol with an earlier request
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// for the same address, it is possible that it will return an
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// initialRequestTime corresponding the earlier request. Since Cycles
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// is unsigned, we can't let this request get profiled below.
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total_lat = Cycles(0);
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}
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DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s %d cycles\n",
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curTick(), m_version, "Seq", llscSuccess ? "Done" : "SC_Failed",
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"", "", printAddress(srequest->pkt->getAddr()), total_lat);
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m_latencyHist.sample(total_lat);
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m_typeLatencyHist[type]->sample(total_lat);
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if (isExternalHit) {
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m_missLatencyHist.sample(total_lat);
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m_missTypeLatencyHist[type]->sample(total_lat);
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if (respondingMach != MachineType_NUM) {
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m_missMachLatencyHist[respondingMach]->sample(total_lat);
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m_missTypeMachLatencyHist[type][respondingMach]->sample(total_lat);
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if ((issued_time <= initialRequestTime) &&
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(initialRequestTime <= forwardRequestTime) &&
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(forwardRequestTime <= firstResponseTime) &&
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(firstResponseTime <= completion_time)) {
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m_IssueToInitialDelayHist[respondingMach]->sample(
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initialRequestTime - issued_time);
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m_InitialToForwardDelayHist[respondingMach]->sample(
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forwardRequestTime - initialRequestTime);
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m_ForwardToFirstResponseDelayHist[respondingMach]->sample(
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firstResponseTime - forwardRequestTime);
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m_FirstResponseToCompletionDelayHist[respondingMach]->sample(
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completion_time - firstResponseTime);
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} else {
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m_IncompleteTimes[respondingMach]++;
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}
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}
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} else {
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m_hitLatencyHist.sample(total_lat);
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m_hitTypeLatencyHist[type]->sample(total_lat);
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if (respondingMach != MachineType_NUM) {
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m_hitMachLatencyHist[respondingMach]->sample(total_lat);
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m_hitTypeMachLatencyHist[type][respondingMach]->sample(total_lat);
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}
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}
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}
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void
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Sequencer::writeCallbackScFail(Addr address, DataBlock& data)
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{
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llscClearMonitor(address);
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writeCallback(address, data);
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}
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void
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Sequencer::writeCallback(Addr address, DataBlock& data,
|
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const bool externalHit, const MachineType mach,
|
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const Cycles initialRequestTime,
|
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const Cycles forwardRequestTime,
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const Cycles firstResponseTime,
|
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const bool noCoales)
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{
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|
//
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// Free the whole list as we assume we have had the exclusive access
|
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// to this cache line when response for the write comes back
|
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//
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assert(address == makeLineAddress(address));
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assert(m_RequestTable.find(address) != m_RequestTable.end());
|
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auto &seq_req_list = m_RequestTable[address];
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|
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// Perform hitCallback on every cpu request made to this cache block while
|
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// ruby request was outstanding. Since only 1 ruby request was made,
|
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// profile the ruby latency once.
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bool ruby_request = true;
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while (!seq_req_list.empty()) {
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SequencerRequest &seq_req = seq_req_list.front();
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// Atomic Request may be executed remotly in the cache hierarchy
|
|
bool atomic_req =
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((seq_req.m_type == RubyRequestType_ATOMIC_RETURN) ||
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(seq_req.m_type == RubyRequestType_ATOMIC_NO_RETURN));
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if ((noCoales || atomic_req) && !ruby_request) {
|
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// Do not process follow-up requests
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// (e.g. if full line no present)
|
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// Reissue to the cache hierarchy
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issueRequest(seq_req.pkt, seq_req.m_second_type);
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break;
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}
|
|
|
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if (ruby_request) {
|
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assert(seq_req.m_type != RubyRequestType_LD);
|
|
assert(seq_req.m_type != RubyRequestType_Load_Linked);
|
|
assert(seq_req.m_type != RubyRequestType_IFETCH);
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assert(seq_req.m_type != RubyRequestType_ATOMIC_RETURN);
|
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assert(seq_req.m_type != RubyRequestType_ATOMIC_NO_RETURN);
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}
|
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|
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// handle write request
|
|
if ((seq_req.m_type != RubyRequestType_LD) &&
|
|
(seq_req.m_type != RubyRequestType_Load_Linked) &&
|
|
(seq_req.m_type != RubyRequestType_IFETCH)) {
|
|
// LL/SC support (tested with ARMv8)
|
|
bool success = true;
|
|
|
|
if (seq_req.m_type != RubyRequestType_Store_Conditional) {
|
|
// Regular stores to addresses being monitored
|
|
// will fail (remove) the monitor entry.
|
|
llscClearMonitor(address);
|
|
} else {
|
|
// Store conditionals must first check the monitor
|
|
// if they will succeed or not
|
|
success = llscStoreConditional(address);
|
|
seq_req.pkt->req->setExtraData(success ? 1 : 0);
|
|
}
|
|
|
|
// Handle SLICC block_on behavior for Locked_RMW accesses. NOTE: the
|
|
// address variable here is assumed to be a line address, so when
|
|
// blocking buffers, must check line addresses.
|
|
if (seq_req.m_type == RubyRequestType_Locked_RMW_Read) {
|
|
// blockOnQueue blocks all first-level cache controller queues
|
|
// waiting on memory accesses for the specified address that go
|
|
// to the specified queue. In this case, a Locked_RMW_Write must
|
|
// go to the mandatory_q before unblocking the first-level
|
|
// controller. This will block standard loads, stores, ifetches,
|
|
// etc.
|
|
m_controller->blockOnQueue(address, m_mandatory_q_ptr);
|
|
} else if (seq_req.m_type == RubyRequestType_Locked_RMW_Write) {
|
|
m_controller->unblock(address);
|
|
}
|
|
|
|
if (ruby_request) {
|
|
recordMissLatency(&seq_req, success, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime);
|
|
}
|
|
|
|
markRemoved();
|
|
hitCallback(&seq_req, data, success, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime, !ruby_request);
|
|
ruby_request = false;
|
|
} else {
|
|
// handle read request
|
|
assert(!ruby_request);
|
|
markRemoved();
|
|
hitCallback(&seq_req, data, true, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime, !ruby_request);
|
|
}
|
|
seq_req_list.pop_front();
|
|
}
|
|
|
|
// free all outstanding requests corresponding to this address
|
|
if (seq_req_list.empty()) {
|
|
m_RequestTable.erase(address);
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::readCallback(Addr address, DataBlock& data,
|
|
bool externalHit, const MachineType mach,
|
|
Cycles initialRequestTime,
|
|
Cycles forwardRequestTime,
|
|
Cycles firstResponseTime)
|
|
{
|
|
//
|
|
// Free up read requests until we hit the first Write request
|
|
// or end of the corresponding list.
|
|
//
|
|
assert(address == makeLineAddress(address));
|
|
assert(m_RequestTable.find(address) != m_RequestTable.end());
|
|
auto &seq_req_list = m_RequestTable[address];
|
|
|
|
// Perform hitCallback on every cpu request made to this cache block while
|
|
// ruby request was outstanding. Since only 1 ruby request was made,
|
|
// profile the ruby latency once.
|
|
bool ruby_request = true;
|
|
while (!seq_req_list.empty()) {
|
|
SequencerRequest &seq_req = seq_req_list.front();
|
|
if (ruby_request) {
|
|
assert((seq_req.m_type == RubyRequestType_LD) ||
|
|
(seq_req.m_type == RubyRequestType_Load_Linked) ||
|
|
(seq_req.m_type == RubyRequestType_IFETCH));
|
|
}
|
|
if ((seq_req.m_type != RubyRequestType_LD) &&
|
|
(seq_req.m_type != RubyRequestType_Load_Linked) &&
|
|
(seq_req.m_type != RubyRequestType_IFETCH) &&
|
|
(seq_req.m_type != RubyRequestType_REPLACEMENT)) {
|
|
// Write request: reissue request to the cache hierarchy
|
|
issueRequest(seq_req.pkt, seq_req.m_second_type);
|
|
break;
|
|
}
|
|
if (ruby_request) {
|
|
recordMissLatency(&seq_req, true, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime);
|
|
}
|
|
markRemoved();
|
|
hitCallback(&seq_req, data, true, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime, !ruby_request);
|
|
ruby_request = false;
|
|
seq_req_list.pop_front();
|
|
}
|
|
|
|
// free all outstanding requests corresponding to this address
|
|
if (seq_req_list.empty()) {
|
|
m_RequestTable.erase(address);
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::atomicCallback(Addr address, DataBlock& data,
|
|
const bool externalHit, const MachineType mach,
|
|
const Cycles initialRequestTime,
|
|
const Cycles forwardRequestTime,
|
|
const Cycles firstResponseTime)
|
|
{
|
|
//
|
|
// Free the first request (an atomic operation) from the list.
|
|
// Then issue the next request to ruby system as we cannot
|
|
// assume the cache line is present in the cache
|
|
// (the opperation could be performed remotly)
|
|
//
|
|
assert(address == makeLineAddress(address));
|
|
assert(m_RequestTable.find(address) != m_RequestTable.end());
|
|
auto &seq_req_list = m_RequestTable[address];
|
|
|
|
// Perform hitCallback only on the first cpu request that
|
|
// issued the ruby request
|
|
bool ruby_request = true;
|
|
while (!seq_req_list.empty()) {
|
|
SequencerRequest &seq_req = seq_req_list.front();
|
|
|
|
if (ruby_request) {
|
|
// Check that the request was an atomic memory operation
|
|
// and record the latency
|
|
assert((seq_req.m_type == RubyRequestType_ATOMIC_RETURN) ||
|
|
(seq_req.m_type == RubyRequestType_ATOMIC_NO_RETURN));
|
|
recordMissLatency(&seq_req, true, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime);
|
|
} else {
|
|
// Read, Write or Atomic request:
|
|
// reissue request to the cache hierarchy
|
|
// (we don't know if op was performed remotly)
|
|
issueRequest(seq_req.pkt, seq_req.m_second_type);
|
|
break;
|
|
}
|
|
|
|
// Atomics clean the monitor entry
|
|
llscClearMonitor(address);
|
|
|
|
markRemoved();
|
|
ruby_request = false;
|
|
hitCallback(&seq_req, data, true, mach, externalHit,
|
|
initialRequestTime, forwardRequestTime,
|
|
firstResponseTime, false);
|
|
seq_req_list.pop_front();
|
|
}
|
|
|
|
// free all outstanding requests corresponding to this address
|
|
if (seq_req_list.empty()) {
|
|
m_RequestTable.erase(address);
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data,
|
|
bool llscSuccess,
|
|
const MachineType mach, const bool externalHit,
|
|
const Cycles initialRequestTime,
|
|
const Cycles forwardRequestTime,
|
|
const Cycles firstResponseTime,
|
|
const bool was_coalesced)
|
|
{
|
|
warn_once("Replacement policy updates recently became the responsibility "
|
|
"of SLICC state machines. Make sure to setMRU() near callbacks "
|
|
"in .sm files!");
|
|
|
|
PacketPtr pkt = srequest->pkt;
|
|
Addr request_address(pkt->getAddr());
|
|
RubyRequestType type = srequest->m_type;
|
|
|
|
if (was_coalesced) {
|
|
// Notify the controller about a coalesced request so it can properly
|
|
// account for it in its hit/miss stats and/or train prefetchers
|
|
// (this is protocol-dependent)
|
|
m_controller->notifyCoalesced(request_address, type, pkt->req,
|
|
data, externalHit);
|
|
}
|
|
|
|
// Load-linked handling
|
|
if (type == RubyRequestType_Load_Linked) {
|
|
Addr line_addr = makeLineAddress(request_address);
|
|
llscLoadLinked(line_addr);
|
|
}
|
|
|
|
DPRINTF(RubyHitMiss, "Cache %s at %#x\n",
|
|
externalHit ? "miss" : "hit",
|
|
printAddress(request_address));
|
|
|
|
// update the data unless it is a non-data-carrying flush
|
|
if (RubySystem::getWarmupEnabled()) {
|
|
data.setData(pkt);
|
|
} else if (!pkt->isFlush()) {
|
|
if ((type == RubyRequestType_LD) ||
|
|
(type == RubyRequestType_IFETCH) ||
|
|
(type == RubyRequestType_RMW_Read) ||
|
|
(type == RubyRequestType_Locked_RMW_Read) ||
|
|
(type == RubyRequestType_Load_Linked) ||
|
|
(type == RubyRequestType_ATOMIC_RETURN)) {
|
|
pkt->setData(
|
|
data.getData(getOffset(request_address), pkt->getSize()));
|
|
|
|
if (type == RubyRequestType_ATOMIC_RETURN) {
|
|
DPRINTF(RubySequencer, "ATOMIC RETURN data %s\n", data);
|
|
} else {
|
|
DPRINTF(RubySequencer, "read data %s\n", data);
|
|
}
|
|
} else if (pkt->req->isSwap()) {
|
|
assert(!pkt->isMaskedWrite());
|
|
std::vector<uint8_t> overwrite_val(pkt->getSize());
|
|
pkt->writeData(&overwrite_val[0]);
|
|
pkt->setData(
|
|
data.getData(getOffset(request_address), pkt->getSize()));
|
|
data.setData(&overwrite_val[0],
|
|
getOffset(request_address), pkt->getSize());
|
|
DPRINTF(RubySequencer, "swap data %s\n", data);
|
|
} else if (pkt->isAtomicOp()) {
|
|
// Set the data in the packet to the old value in the cache
|
|
pkt->setData(
|
|
data.getData(getOffset(request_address), pkt->getSize()));
|
|
DPRINTF(RubySequencer, "AMO original data %s\n", data);
|
|
// execute AMO operation
|
|
(*(pkt->getAtomicOp()))(
|
|
data.getDataMod(getOffset(request_address)));
|
|
DPRINTF(RubySequencer, "AMO new data %s\n", data);
|
|
} else if (type != RubyRequestType_Store_Conditional || llscSuccess) {
|
|
// Types of stores set the actual data here, apart from
|
|
// failed Store Conditional requests
|
|
data.setData(pkt);
|
|
DPRINTF(RubySequencer, "set data %s\n", data);
|
|
}
|
|
}
|
|
|
|
// If using the RubyTester, update the RubyTester sender state's
|
|
// subBlock with the recieved data. The tester will later access
|
|
// this state.
|
|
if (m_usingRubyTester) {
|
|
DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
|
|
pkt->cmdString(), pkt->getAddr());
|
|
RubyTester::SenderState* testerSenderState =
|
|
pkt->findNextSenderState<RubyTester::SenderState>();
|
|
assert(testerSenderState);
|
|
testerSenderState->subBlock.mergeFrom(data);
|
|
}
|
|
|
|
RubySystem *rs = m_ruby_system;
|
|
if (RubySystem::getWarmupEnabled()) {
|
|
assert(pkt->req);
|
|
delete pkt;
|
|
rs->m_cache_recorder->enqueueNextFetchRequest();
|
|
} else if (RubySystem::getCooldownEnabled()) {
|
|
delete pkt;
|
|
rs->m_cache_recorder->enqueueNextFlushRequest();
|
|
} else {
|
|
ruby_hit_callback(pkt);
|
|
testDrainComplete();
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::unaddressedCallback(Addr unaddressedReqId,
|
|
RubyRequestType reqType,
|
|
const MachineType mach,
|
|
const Cycles initialRequestTime,
|
|
const Cycles forwardRequestTime,
|
|
const Cycles firstResponseTime)
|
|
{
|
|
DPRINTF(RubySequencer, "unaddressedCallback ID:%08x type:%d\n",
|
|
unaddressedReqId, reqType);
|
|
|
|
switch (reqType) {
|
|
case RubyRequestType_TLBI_EXT_SYNC:
|
|
{
|
|
// This should trigger the CPU to wait for stale translations
|
|
// and send an EXT_SYNC_COMP once complete.
|
|
|
|
// Don't look for the ID in our requestTable.
|
|
// It won't be there because we didn't request this Sync
|
|
ruby_stale_translation_callback(unaddressedReqId);
|
|
break;
|
|
}
|
|
case RubyRequestType_TLBI:
|
|
case RubyRequestType_TLBI_SYNC:
|
|
{
|
|
// These signal that a TLBI operation that this core initiated
|
|
// of the respective type (TLBI or Sync) has finished.
|
|
|
|
assert(m_UnaddressedRequestTable.find(unaddressedReqId)
|
|
!= m_UnaddressedRequestTable.end());
|
|
|
|
{
|
|
SequencerRequest &seq_req =
|
|
m_UnaddressedRequestTable.at(unaddressedReqId);
|
|
assert(seq_req.m_type == reqType);
|
|
|
|
PacketPtr pkt = seq_req.pkt;
|
|
|
|
ruby_unaddressed_callback(pkt);
|
|
testDrainComplete();
|
|
}
|
|
|
|
m_UnaddressedRequestTable.erase(unaddressedReqId);
|
|
break;
|
|
}
|
|
default:
|
|
panic("Unexpected TLBI RubyRequestType");
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::completeHitCallback(std::vector<PacketPtr> & mylist)
|
|
{
|
|
for (auto& pkt : mylist) {
|
|
// When Ruby is in warmup or cooldown phase, the requests come
|
|
// from the cache recorder. They do not track which port to use
|
|
// and do not need to send the response back
|
|
if (!RubySystem::getWarmupEnabled()
|
|
&& !RubySystem::getCooldownEnabled()) {
|
|
RubyPort::SenderState *ss =
|
|
safe_cast<RubyPort::SenderState *>(pkt->senderState);
|
|
MemResponsePort *port = ss->port;
|
|
assert(port != NULL);
|
|
|
|
pkt->senderState = ss->predecessor;
|
|
|
|
if (pkt->cmd != MemCmd::WriteReq) {
|
|
// for WriteReq, we keep the original senderState until
|
|
// writeCompleteCallback
|
|
delete ss;
|
|
}
|
|
|
|
port->hitCallback(pkt);
|
|
trySendRetries();
|
|
}
|
|
}
|
|
|
|
RubySystem *rs = m_ruby_system;
|
|
if (RubySystem::getWarmupEnabled()) {
|
|
rs->m_cache_recorder->enqueueNextFetchRequest();
|
|
} else if (RubySystem::getCooldownEnabled()) {
|
|
rs->m_cache_recorder->enqueueNextFlushRequest();
|
|
} else {
|
|
testDrainComplete();
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::invL1Callback()
|
|
{
|
|
// Since L1 invalidate is currently done with paddr = 0
|
|
assert(m_cache_inv_pkt && m_num_pending_invs > 0);
|
|
|
|
m_num_pending_invs--;
|
|
|
|
if (m_num_pending_invs == 0) {
|
|
std::vector<PacketPtr> pkt_list { m_cache_inv_pkt };
|
|
m_cache_inv_pkt = nullptr;
|
|
completeHitCallback(pkt_list);
|
|
}
|
|
}
|
|
|
|
void
|
|
Sequencer::invL1()
|
|
{
|
|
int size = m_dataCache_ptr->getNumBlocks();
|
|
DPRINTF(RubySequencer,
|
|
"There are %d Invalidations outstanding before Cache Walk\n",
|
|
m_num_pending_invs);
|
|
// Walk the cache
|
|
for (int i = 0; i < size; i++) {
|
|
Addr addr = m_dataCache_ptr->getAddressAtIdx(i);
|
|
// Evict Read-only data
|
|
RubyRequestType request_type = RubyRequestType_REPLACEMENT;
|
|
std::shared_ptr<RubyRequest> msg = std::make_shared<RubyRequest>(
|
|
clockEdge(), addr, 0, 0,
|
|
request_type, RubyAccessMode_Supervisor,
|
|
nullptr);
|
|
DPRINTF(RubySequencer, "Evicting addr 0x%x\n", addr);
|
|
assert(m_mandatory_q_ptr != NULL);
|
|
Tick latency = cyclesToTicks(
|
|
m_controller->mandatoryQueueLatency(request_type));
|
|
m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
|
|
m_num_pending_invs++;
|
|
}
|
|
DPRINTF(RubySequencer,
|
|
"There are %d Invalidations outstanding after Cache Walk\n",
|
|
m_num_pending_invs);
|
|
}
|
|
|
|
bool
|
|
Sequencer::empty() const
|
|
{
|
|
return m_RequestTable.empty() &&
|
|
m_UnaddressedRequestTable.empty();
|
|
}
|
|
|
|
RequestStatus
|
|
Sequencer::makeRequest(PacketPtr pkt)
|
|
{
|
|
// HTM abort signals must be allowed to reach the Sequencer
|
|
// the same cycle they are issued. They cannot be retried.
|
|
if ((m_outstanding_count >= m_max_outstanding_requests) &&
|
|
!pkt->req->isHTMAbort()) {
|
|
return RequestStatus_BufferFull;
|
|
}
|
|
|
|
RubyRequestType primary_type = RubyRequestType_NULL;
|
|
RubyRequestType secondary_type = RubyRequestType_NULL;
|
|
|
|
if (pkt->isLLSC()) {
|
|
// LL/SC instructions need to be handled carefully by the cache
|
|
// coherence protocol to ensure they follow the proper semantics. In
|
|
// particular, by identifying the operations as atomic, the protocol
|
|
// should understand that migratory sharing optimizations should not
|
|
// be performed (i.e. a load between the LL and SC should not steal
|
|
// away exclusive permission).
|
|
//
|
|
// The following logic works correctly with the semantics
|
|
// of armV8 LDEX/STEX instructions.
|
|
|
|
if (pkt->isWrite()) {
|
|
DPRINTF(RubySequencer, "Issuing SC\n");
|
|
primary_type = RubyRequestType_Store_Conditional;
|
|
#if defined (PROTOCOL_MESI_Three_Level) || defined (PROTOCOL_MESI_Three_Level_HTM)
|
|
secondary_type = RubyRequestType_Store_Conditional;
|
|
#else
|
|
secondary_type = RubyRequestType_ST;
|
|
#endif
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing LL\n");
|
|
assert(pkt->isRead());
|
|
primary_type = RubyRequestType_Load_Linked;
|
|
secondary_type = RubyRequestType_LD;
|
|
}
|
|
} else if (pkt->req->isLockedRMW()) {
|
|
//
|
|
// x86 locked instructions are translated to store cache coherence
|
|
// requests because these requests should always be treated as read
|
|
// exclusive operations and should leverage any migratory sharing
|
|
// optimization built into the protocol.
|
|
//
|
|
if (pkt->isWrite()) {
|
|
DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
|
|
primary_type = RubyRequestType_Locked_RMW_Write;
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
|
|
assert(pkt->isRead());
|
|
primary_type = RubyRequestType_Locked_RMW_Read;
|
|
}
|
|
secondary_type = RubyRequestType_ST;
|
|
} else if (pkt->req->isTlbiCmd()) {
|
|
primary_type = secondary_type = tlbiCmdToRubyRequestType(pkt);
|
|
DPRINTF(RubySequencer, "Issuing TLBI\n");
|
|
#if defined (PROTOCOL_CHI)
|
|
} else if (pkt->isAtomicOp()) {
|
|
if (pkt->req->isAtomicReturn()){
|
|
DPRINTF(RubySequencer, "Issuing ATOMIC RETURN \n");
|
|
primary_type = secondary_type =
|
|
RubyRequestType_ATOMIC_RETURN;
|
|
} else {
|
|
DPRINTF(RubySequencer, "Issuing ATOMIC NO RETURN\n");
|
|
primary_type = secondary_type =
|
|
RubyRequestType_ATOMIC_NO_RETURN;
|
|
|
|
}
|
|
#endif
|
|
} else {
|
|
//
|
|
// To support SwapReq, we need to check isWrite() first: a SwapReq
|
|
// should always be treated like a write, but since a SwapReq implies
|
|
// both isWrite() and isRead() are true, check isWrite() first here.
|
|
//
|
|
if (pkt->isWrite()) {
|
|
//
|
|
// Note: M5 packets do not differentiate ST from RMW_Write
|
|
//
|
|
primary_type = secondary_type = RubyRequestType_ST;
|
|
} else if (pkt->isRead()) {
|
|
// hardware transactional memory commands
|
|
if (pkt->req->isHTMCmd()) {
|
|
primary_type = secondary_type = htmCmdToRubyRequestType(pkt);
|
|
} else if (pkt->req->isInstFetch()) {
|
|
primary_type = secondary_type = RubyRequestType_IFETCH;
|
|
} else {
|
|
if (pkt->req->isReadModifyWrite()) {
|
|
primary_type = RubyRequestType_RMW_Read;
|
|
secondary_type = RubyRequestType_ST;
|
|
} else {
|
|
primary_type = secondary_type = RubyRequestType_LD;
|
|
}
|
|
}
|
|
} else if (pkt->isFlush()) {
|
|
primary_type = secondary_type = RubyRequestType_FLUSH;
|
|
} else if (pkt->cmd == MemCmd::MemSyncReq) {
|
|
primary_type = secondary_type = RubyRequestType_REPLACEMENT;
|
|
assert(!m_cache_inv_pkt);
|
|
m_cache_inv_pkt = pkt;
|
|
invL1();
|
|
} else {
|
|
panic("Unsupported ruby packet type\n");
|
|
}
|
|
}
|
|
|
|
// Check if the line is blocked for a Locked_RMW
|
|
if (!pkt->req->isMemMgmt() &&
|
|
m_controller->isBlocked(makeLineAddress(pkt->getAddr())) &&
|
|
(primary_type != RubyRequestType_Locked_RMW_Write)) {
|
|
// Return that this request's cache line address aliases with
|
|
// a prior request that locked the cache line. The request cannot
|
|
// proceed until the cache line is unlocked by a Locked_RMW_Write
|
|
return RequestStatus_Aliased;
|
|
}
|
|
|
|
RequestStatus status = insertRequest(pkt, primary_type, secondary_type);
|
|
|
|
// It is OK to receive RequestStatus_Aliased, it can be considered Issued
|
|
if (status != RequestStatus_Ready && status != RequestStatus_Aliased)
|
|
return status;
|
|
// non-aliased with any existing request in the request table, just issue
|
|
// to the cache
|
|
if (status != RequestStatus_Aliased)
|
|
issueRequest(pkt, secondary_type);
|
|
|
|
// TODO: issue hardware prefetches here
|
|
return RequestStatus_Issued;
|
|
}
|
|
|
|
void
|
|
Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
|
|
{
|
|
assert(pkt != NULL);
|
|
ContextID proc_id = pkt->req->hasContextId() ?
|
|
pkt->req->contextId() : InvalidContextID;
|
|
|
|
ContextID core_id = coreId();
|
|
|
|
// If valid, copy the pc to the ruby request
|
|
Addr pc = 0;
|
|
if (pkt->req->hasPC()) {
|
|
pc = pkt->req->getPC();
|
|
}
|
|
|
|
// check if the packet has data as for example prefetch and flush
|
|
// requests do not
|
|
std::shared_ptr<RubyRequest> msg;
|
|
if (pkt->req->isMemMgmt()) {
|
|
msg = std::make_shared<RubyRequest>(clockEdge(),
|
|
pc, secondary_type,
|
|
RubyAccessMode_Supervisor, pkt,
|
|
proc_id, core_id);
|
|
|
|
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %s\n",
|
|
curTick(), m_version, "Seq", "Begin", "", "",
|
|
RubyRequestType_to_string(secondary_type));
|
|
|
|
if (pkt->req->isTlbiCmd()) {
|
|
msg->m_isTlbi = true;
|
|
switch (secondary_type) {
|
|
case RubyRequestType_TLBI_EXT_SYNC_COMP:
|
|
msg->m_tlbiTransactionUid = pkt->req->getExtraData();
|
|
break;
|
|
case RubyRequestType_TLBI:
|
|
case RubyRequestType_TLBI_SYNC:
|
|
msg->m_tlbiTransactionUid = \
|
|
getCurrentUnaddressedTransactionID();
|
|
break;
|
|
default:
|
|
panic("Unexpected TLBI RubyRequestType");
|
|
}
|
|
DPRINTF(RubySequencer, "Issuing TLBI %016x\n",
|
|
msg->m_tlbiTransactionUid);
|
|
}
|
|
} else {
|
|
msg = std::make_shared<RubyRequest>(clockEdge(), pkt->getAddr(),
|
|
pkt->getSize(), pc, secondary_type,
|
|
RubyAccessMode_Supervisor, pkt,
|
|
PrefetchBit_No, proc_id, core_id);
|
|
|
|
if (pkt->isAtomicOp() &&
|
|
((secondary_type == RubyRequestType_ATOMIC_RETURN) ||
|
|
(secondary_type == RubyRequestType_ATOMIC_NO_RETURN))){
|
|
// Create the blocksize, access mask and atomicops
|
|
uint32_t offset = getOffset(pkt->getAddr());
|
|
std::vector<std::pair<int,AtomicOpFunctor*>> atomicOps;
|
|
atomicOps.push_back(std::make_pair<int,AtomicOpFunctor*>
|
|
(offset, pkt->getAtomicOp()));
|
|
|
|
msg->setWriteMask(offset, pkt->getSize(), atomicOps);
|
|
}
|
|
|
|
DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n",
|
|
curTick(), m_version, "Seq", "Begin", "", "",
|
|
printAddress(msg->getPhysicalAddress()),
|
|
RubyRequestType_to_string(secondary_type));
|
|
}
|
|
|
|
// hardware transactional memory
|
|
// If the request originates in a transaction,
|
|
// then mark the Ruby message as such.
|
|
if (pkt->isHtmTransactional()) {
|
|
msg->m_htmFromTransaction = true;
|
|
msg->m_htmTransactionUid = pkt->getHtmTransactionUid();
|
|
}
|
|
|
|
Tick latency = cyclesToTicks(
|
|
m_controller->mandatoryQueueLatency(secondary_type));
|
|
assert(latency > 0);
|
|
|
|
assert(m_mandatory_q_ptr != NULL);
|
|
m_mandatory_q_ptr->enqueue(msg, clockEdge(), latency);
|
|
}
|
|
|
|
template <class KEY, class VALUE>
|
|
std::ostream &
|
|
operator<<(std::ostream &out, const std::unordered_map<KEY, VALUE> &map)
|
|
{
|
|
for (const auto &table_entry : map) {
|
|
out << "[ " << table_entry.first << " =";
|
|
for (const auto &seq_req : table_entry.second) {
|
|
out << " " << RubyRequestType_to_string(seq_req.m_second_type);
|
|
}
|
|
}
|
|
out << " ]";
|
|
|
|
return out;
|
|
}
|
|
|
|
void
|
|
Sequencer::print(std::ostream& out) const
|
|
{
|
|
out << "[Sequencer: " << m_version
|
|
<< ", outstanding requests: " << m_outstanding_count
|
|
<< ", request table: " << m_RequestTable
|
|
<< "]";
|
|
}
|
|
|
|
void
|
|
Sequencer::recordRequestType(SequencerRequestType requestType) {
|
|
DPRINTF(RubyStats, "Recorded statistic: %s\n",
|
|
SequencerRequestType_to_string(requestType));
|
|
}
|
|
|
|
void
|
|
Sequencer::evictionCallback(Addr address)
|
|
{
|
|
llscClearMonitor(address);
|
|
ruby_eviction_callback(address);
|
|
}
|
|
|
|
void
|
|
Sequencer::incrementUnaddressedTransactionCnt()
|
|
{
|
|
m_unaddressedTransactionCnt++;
|
|
// Limit m_unaddressedTransactionCnt to 32 bits,
|
|
// top 32 bits should always be zeroed out
|
|
uint64_t aligned_txid = \
|
|
m_unaddressedTransactionCnt << RubySystem::getBlockSizeBits();
|
|
|
|
if (aligned_txid > 0xFFFFFFFFull) {
|
|
m_unaddressedTransactionCnt = 0;
|
|
}
|
|
}
|
|
|
|
uint64_t
|
|
Sequencer::getCurrentUnaddressedTransactionID() const
|
|
{
|
|
return (
|
|
uint64_t(m_version & 0xFFFFFFFF) << 32) |
|
|
(m_unaddressedTransactionCnt << RubySystem::getBlockSizeBits()
|
|
);
|
|
}
|
|
|
|
} // namespace ruby
|
|
} // namespace gem5
|