Ali Saidi 79f81e2641 cpu: Fix O3 issuse with load+barrier instructions. ...

Fix a problem in the O3 CPU for instructions that are both
memory loads and memory barriers (e.g. load acquire) and
to uncacheable memory. This combination can confuse the
commit stage into commitng an instruction that hasn't
executed and got it's value yet. At the same time refactor
the code slightly to remove duplication between two of
the cases.

2013-10-31 13:41:13 -05:00

..

arch

arm: Accomodate function name changes in newer linux kernels

2013-10-17 10:20:45 -05:00

base

base: Fix a potential race in PollQueue::setupAsyncIO

2013-10-07 16:03:15 +02:00

cpu

cpu: Fix O3 issuse with load+barrier instructions.

2013-10-31 13:41:13 -05:00

dev

arm: Add a 'clear PPI' method to gic_pl390

2013-10-17 10:20:45 -05:00

doc

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

mem

ruby: set SenderMachine in messages of MOESI_CMP_directory

2013-10-30 10:35:06 -05:00

proto

base: Avoid size limitation on protobuf coded streams

2013-05-30 12:53:53 -04:00

python

config: Fix ommission of number base in ethernet address param

2013-10-17 10:20:45 -05:00

sim

sim: Fix undefined behavior in the pseudo-inst interface

2013-09-18 17:08:35 +02:00

unittest

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

build: Place proto output in the same directory, also for EXTRAS

2013-10-17 10:20:45 -05:00