6687265fe2
Change-Id: Icfba8e23b5f6820a6ddefe1a50abbe5f8825b7b5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25444 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
128 lines
5.2 KiB
Python
128 lines
5.2 KiB
Python
# Copyright (c) 2010, 2017 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.SimObject import SimObject
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from m5.defines import buildEnv
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from m5.params import *
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from m5.objects.FuncUnit import *
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class IntALU(FUDesc):
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opList = [ OpDesc(opClass='IntAlu') ]
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count = 6
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class IntMultDiv(FUDesc):
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opList = [ OpDesc(opClass='IntMult', opLat=3),
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OpDesc(opClass='IntDiv', opLat=20, pipelined=False) ]
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# DIV and IDIV instructions in x86 are implemented using a loop which
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# issues division microops. The latency of these microops should really be
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# one (or a small number) cycle each since each of these computes one bit
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# of the quotient.
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if buildEnv['TARGET_ISA'] in ('x86'):
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opList[1].opLat=1
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count=2
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class FP_ALU(FUDesc):
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opList = [ OpDesc(opClass='FloatAdd', opLat=2),
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OpDesc(opClass='FloatCmp', opLat=2),
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OpDesc(opClass='FloatCvt', opLat=2) ]
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count = 4
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class FP_MultDiv(FUDesc):
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opList = [ OpDesc(opClass='FloatMult', opLat=4),
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OpDesc(opClass='FloatMultAcc', opLat=5),
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OpDesc(opClass='FloatMisc', opLat=3),
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OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
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OpDesc(opClass='FloatSqrt', opLat=24, pipelined=False) ]
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count = 2
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class SIMD_Unit(FUDesc):
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opList = [ OpDesc(opClass='SimdAdd'),
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OpDesc(opClass='SimdAddAcc'),
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OpDesc(opClass='SimdAlu'),
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OpDesc(opClass='SimdCmp'),
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OpDesc(opClass='SimdCvt'),
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OpDesc(opClass='SimdMisc'),
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OpDesc(opClass='SimdMult'),
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OpDesc(opClass='SimdMultAcc'),
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OpDesc(opClass='SimdShift'),
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OpDesc(opClass='SimdShiftAcc'),
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OpDesc(opClass='SimdDiv'),
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OpDesc(opClass='SimdSqrt'),
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OpDesc(opClass='SimdFloatAdd'),
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OpDesc(opClass='SimdFloatAlu'),
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OpDesc(opClass='SimdFloatCmp'),
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OpDesc(opClass='SimdFloatCvt'),
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OpDesc(opClass='SimdFloatDiv'),
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OpDesc(opClass='SimdFloatMisc'),
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OpDesc(opClass='SimdFloatMult'),
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OpDesc(opClass='SimdFloatMultAcc'),
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OpDesc(opClass='SimdFloatSqrt'),
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OpDesc(opClass='SimdReduceAdd'),
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OpDesc(opClass='SimdReduceAlu'),
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OpDesc(opClass='SimdReduceCmp'),
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OpDesc(opClass='SimdFloatReduceAdd'),
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OpDesc(opClass='SimdFloatReduceCmp') ]
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count = 4
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class PredALU(FUDesc):
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opList = [ OpDesc(opClass='SimdPredAlu') ]
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count = 1
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class ReadPort(FUDesc):
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opList = [ OpDesc(opClass='MemRead'),
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OpDesc(opClass='FloatMemRead') ]
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count = 0
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class WritePort(FUDesc):
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opList = [ OpDesc(opClass='MemWrite'),
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OpDesc(opClass='FloatMemWrite') ]
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count = 0
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class RdWrPort(FUDesc):
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opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite'),
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OpDesc(opClass='FloatMemRead'), OpDesc(opClass='FloatMemWrite')]
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count = 4
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class IprPort(FUDesc):
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opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ]
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count = 1
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