Steve Reinhardt 6677b9122a mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW ...

Makes x86-style locked operations even more distinct from
LLSC operations.  Using "locked" by itself should be
obviously ambiguous now.

2015-03-23 16:14:20 -07:00

..

probes

cpu: commit probe notification on every microop or macroop

2015-01-20 14:15:27 -06:00

atomic.cc

mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMW

2015-03-23 16:14:20 -07:00

atomic.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

AtomicSimpleCPU.py

cpu: use probes infrastructure to do simpoint profiling

2014-09-20 17:17:43 -04:00

base.cc

arm: Fixes based on UBSan and static analysis

2014-11-14 03:53:51 -05:00

base.hh

arch: Make readMiscRegNoEffect const throughout

2015-02-16 03:33:28 -05:00

BaseSimpleCPU.py

cpu: simple: Add support for using branch predictors

2014-02-09 20:49:28 +01:00

SConscript

scons: rename TraceFlags to DebugFlags

2011-06-02 17:36:21 -07:00

SConsopts

arch, cpu: Factor out the ExecContext into a proper base class

2014-09-03 07:42:22 -04:00

timing.cc

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

timing.hh

mem: Split port retry for all different packet classes

2015-03-02 04:00:35 -05:00

TimingSimpleCPU.py

cpu: Add CPU metadata om the Python classes

2013-02-15 17:40:08 -05:00