413b4e7431
We know data is little endian, so we can use those accessors explicitly. Change-Id: I09aa7f1e525ad1346e932ce4a772b64bf59dc350 Reviewed-on: https://gem5-review.googlesource.com/c/13456 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
104 lines
3.0 KiB
C++
104 lines
3.0 KiB
C++
/*
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* Copyright (c) 2008 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "dev/x86/i8254.hh"
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#include "debug/I8254.hh"
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#include "dev/x86/intdev.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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void
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X86ISA::I8254::counterInterrupt(unsigned int num)
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{
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DPRINTF(I8254, "Interrupt from counter %d.\n", num);
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if (num == 0) {
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intPin->raise();
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//XXX This is a hack.
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intPin->lower();
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}
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}
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Tick
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X86ISA::I8254::read(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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Addr offset = pkt->getAddr() - pioAddr;
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if (offset < 3) {
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pkt->setLE(pit.readCounter(offset));
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} else if (offset == 3) {
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pkt->setLE(uint8_t(-1));
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} else {
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panic("Read from undefined i8254 register.\n");
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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Tick
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X86ISA::I8254::write(PacketPtr pkt)
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{
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assert(pkt->getSize() == 1);
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Addr offset = pkt->getAddr() - pioAddr;
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if (offset < 3) {
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pit.writeCounter(offset, pkt->getLE<uint8_t>());
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} else if (offset == 3) {
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pit.writeControl(pkt->getLE<uint8_t>());
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} else {
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panic("Write to undefined i8254 register.\n");
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}
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pkt->makeAtomicResponse();
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return latency;
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}
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void
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X86ISA::I8254::serialize(CheckpointOut &cp) const
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{
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pit.serialize("pit", cp);
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}
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void
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X86ISA::I8254::unserialize(CheckpointIn &cp)
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{
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pit.unserialize("pit", cp);
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}
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void
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X86ISA::I8254::startup()
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{
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pit.startup();
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}
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X86ISA::I8254 *
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I8254Params::create()
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{
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return new X86ISA::I8254(this);
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}
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