Steve Reinhardt 659aef3eb8 Fix formatting and comments in cache_impl.hh ...

--HG--
extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41

2008-01-02 12:15:48 -08:00

..

cache

Fix formatting and comments in cache_impl.hh

2008-01-02 12:15:48 -08:00

config

Backing in more changsets, getting closer to compile

2006-06-28 14:35:00 -04:00

bridge.cc

Make ports that aren't connected to anything fail more gracefully.

2007-11-28 14:39:19 -08:00

bridge.hh

Merge with head

2007-08-26 21:45:40 -07:00

Bridge.py

DMA: Add IOCache and fix bus bridge to optionally only send requests one

2007-08-10 16:14:01 -04:00

bus.cc

mem: clean up bus/cache DPRINTFs a bit

2007-09-16 16:46:38 -07:00

bus.hh

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

Bus.py

Move SimObject python files alongside the C++ and fix

2007-05-27 19:21:17 -07:00

dram.cc

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

dram.hh

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

mem_object.cc

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

mem_object.hh

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

MemObject.py

Major changes to how SimObjects are created and initialized. Almost all

2007-07-23 21:51:38 -07:00

packet_access.hh

Make byteswap work correctly on Twin??_t types.

2007-03-07 17:46:04 +00:00

packet.cc

Merge with head

2007-08-26 21:45:40 -07:00

packet.hh

Merge with head

2007-08-26 21:45:40 -07:00

page_table.cc

Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once.

2007-11-14 23:42:08 -05:00

page_table.hh

TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.

2007-10-25 19:04:44 -07:00

physical.cc

Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access.

2007-11-19 18:23:43 -05:00

physical.hh

Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access.

2007-11-19 18:23:43 -05:00

PhysicalMemory.py

DRAM: Make latency parameters be Param.Latency instead of ints.

2007-11-01 17:30:50 -04:00

port_impl.hh

Put the ProcessInfo and StackTrace objects into the ISA namespaces.

2006-11-08 00:52:04 -05:00

port.cc

Make ports that aren't connected to anything fail more gracefully.

2007-11-28 14:39:19 -08:00

port.hh

Make ports that aren't connected to anything fail more gracefully.

2007-11-28 14:39:19 -08:00

request.hh

Add in files from merge-bare-iron, get them compiling in FS and SE mode

2007-11-13 16:58:16 -05:00

SConscript

Traceflags: Add SCons function to created a traceflag instead of having one file with them all.

2007-10-31 01:21:54 -04:00

tport.cc

MemorySystem: Fix the use of ?: to produce correct results.

2007-08-12 19:43:54 -04:00

tport.hh

memory system: fix functional access bug.

2007-07-29 20:17:03 -07:00

translating_port.cc

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

translating_port.hh

fix the translating ports so it can add a page on a fault

2007-05-09 15:37:46 -04:00

vport.cc

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00

vport.hh

implement vtophys and 32bit gdb support

2007-02-18 19:57:46 -05:00