David Hashe 8f71e667b3 cpu: Fixed a bug on where to fetch the next instruction from ...

Figure out if the next instruction to fetch comes from the micro-op ROM
or not. Otherwise, wrong instructions may be fetched.

2015-07-20 09:15:18 -05:00

..

checker

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

kvm

sim: Refactor and simplify the drain API

2015-07-07 09:51:05 +01:00

minor

cpu: Update debug message from Fetch1 isDrained() in Minor

2015-07-31 17:04:59 +01:00

nocpu

arch, cpu: Factor out the ExecContext into a proper base class

2014-09-03 07:42:22 -04:00

o3

cpu: Fixed a bug on where to fetch the next instruction from

2015-07-20 09:15:18 -05:00

pred

cpu: re-organizes the branch predictor structure.

2015-04-13 17:33:57 -05:00

simple

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

testers

ruby: replace global g_abs_controls with per-RubySystem var

2015-07-10 16:05:24 -05:00

activity.cc

Fix: Address a few benign memory leaks

2012-07-09 12:35:30 -04:00

activity.hh

cpu: Useful getters for ActivityRecorder

2014-05-09 18:58:48 -04:00

base_dyn_inst_impl.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

base_dyn_inst.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

base.cc

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

base.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

BaseCPU.py

mem: Move crossbar default latencies to subclasses

2015-03-02 04:00:47 -05:00

CheckerCPU.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

cpuevent.cc

…

cpuevent.hh

…

CPUTracers.py

cpu: Put all CPU instruction tracers in a single file

2015-01-25 07:22:17 -05:00

decode_cache.hh

ISA,CPU: Generalize and split out the components of the decode cache.

2012-05-26 13:45:12 -07:00

dummy_checker.cc

sim: Add the notion of clock domains to all ClockedObjects

2013-06-27 05:49:49 -04:00

dummy_checker.hh

cpu: Add header files for checker CPUs

2012-11-02 11:32:01 -05:00

DummyChecker.py

cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy

2013-02-15 17:40:08 -05:00

exec_context.cc

arch, cpu: Factor out the ExecContext into a proper base class

2014-09-03 07:42:22 -04:00

exec_context.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

exetrace.cc

sim: Clean up InstRecord

2015-01-25 07:22:44 -05:00

exetrace.hh

cpu: Remove all notion that we know when the cpu is misspeculating.

2015-01-25 07:22:26 -05:00

func_unit.cc

cpu: Fix issue identified by UBSan

2015-07-30 03:41:22 -04:00

func_unit.hh

cpu: Fix issue identified by UBSan

2015-07-30 03:41:22 -04:00

FuncUnit.py

cpu: o3: replace issueLatency with bool pipelined

2015-04-29 22:35:22 -05:00

inst_pb_trace.cc

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

inst_pb_trace.hh

cpu: Fix InstPBTrace inheritance

2015-03-26 11:16:43 -04:00

inst_seq.hh

…

InstPBTrace.py

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

inteltrace.cc

gcc: Clean-up of non-C++0x compliant code, first steps

2012-03-19 06:36:09 -04:00

inteltrace.hh

cpu: Remove all notion that we know when the cpu is misspeculating.

2015-01-25 07:22:26 -05:00

intr_control_noisa.cc

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

intr_control.cc

SE/FS: Get rid of FULL_SYSTEM in the CPU directory.

2011-11-18 01:33:28 -08:00

intr_control.hh

arch: Header clean up for NOISA resurrection

2013-09-04 13:22:55 -04:00

IntrControl.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

nativetrace.cc

…

nativetrace.hh

cpu: Remove all notion that we know when the cpu is misspeculating.

2015-01-25 07:22:26 -05:00

op_class.hh

cpu: Work around gcc 4.9 issues with Num_OpClasses

2015-05-05 03:22:19 -04:00

pc_event.cc

arm: Enable support for triggering a sim panic on kernel panics

2013-04-22 13:20:31 -04:00

pc_event.hh

arm: Enable support for triggering a sim panic on kernel panics

2013-04-22 13:20:31 -04:00

profile.cc

…

profile.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

quiesce_event.cc

…

quiesce_event.hh

clang: Enable compiling gem5 using clang 2.9 and 3.0

2012-01-31 12:05:52 -05:00

reg_class.cc

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

reg_class.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

SConscript

cpu: add support for outputing a protobuf formatted CPU trace

2015-02-16 03:32:38 -05:00

simple_thread.cc

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

simple_thread.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

smt.hh

…

static_inst_fwd.hh

cpu: Don't forward declare RefCountingPtr

2014-08-13 06:57:26 -04:00

static_inst.cc

cpu: Add flag name printing to StaticInst

2014-05-09 18:58:47 -04:00

static_inst.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

StaticInstFlags.py

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

thread_context.cc

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

thread_context.hh

revert 5af8f40d8f2c

2015-07-28 01:58:04 -05:00

thread_state.cc

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

thread_state.hh

sim: Refactor the serialization base class

2015-07-07 09:51:03 +01:00

timebuf.hh

cpu: Timebuf const accessors

2014-05-09 18:58:47 -04:00

timing_expr.cc

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

timing_expr.hh

arch: Use const StaticInstPtr references where possible

2014-09-27 09:08:36 -04:00

TimingExpr.py

cpu: `Minor' in-order CPU model

2014-07-23 16:09:04 -05:00

translation.hh

mem, cpu: Add a separate flag for strictly ordered memory

2015-05-05 03:22:33 -04:00