Giacomo Travaglini 41b339367c sim-se: Set ArmProcess64 hwcaps depending on ID regs ...

ArmProcess64 needs to query AArch64 ID registers to check which hw
capability is going to report in the appropriate aux vector's entry.

Change-Id: I1e1294b831e902226f9b162f25e841e53b940454
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13164
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

2018-10-02 21:12:43 +00:00

..

alpha

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

arm

sim-se: Set ArmProcess64 hwcaps depending on ID regs

2018-10-02 21:12:43 +00:00

generic

arch: Fix unserialization of VectorReg value

2018-10-02 11:51:44 +00:00

hsail

misc: Using smart pointers for memory Requests

2018-06-11 16:55:30 +00:00

mips

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

null

scons: Stop generating inc.d in the isa parser.

2017-10-17 18:57:50 +00:00

power

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

riscv

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

sparc

syscall_emul: expand AuxVector class

2018-09-19 20:51:17 +00:00

x86

syscall_emul: implement dir-related syscalls

2018-09-19 20:54:04 +00:00

isa_parser.py

arch, arm: Fix implicit-fallthrough GCC warnings

2018-03-20 20:17:00 +00:00

micro_asm_test.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

micro_asm.py

scons: Switch from the print statement to the print function.

2018-03-06 23:39:01 +00:00

SConscript

arch: Remove the "arch/tlb.hh" switching header.

2018-01-23 20:39:24 +00:00