0b54ad277f
The purpose of the gem5 components library is to provide gem5 users a standard set of common and useful gem5 components pre-built to add to their experiments. The gem5 components library adopts a modular architecture design with the goal of components being easy to add and remove from designs, and extendable as needed. E.g., any Memory system should be interchangable with any other, and if not a helpful error messages should be raised. Examples of using the gem5 components library can be found in `configs/example/components-library`. Important Disclaimer: This is a pre-alpha release of the gem5 components library. The purpose of this release is to get some community feedback on this new component of gem5. Though some testing has been done, we expect regular fixes and improvements until this is in a stable state. The components library has been formatted with Python Black; typing has been checked with MyPy; and the library has been tested with the scripts in `configs/example/components-libary`. More rigorous tests are to be added in future revisions. More detailed documentation will appear in future revisions. Jira Ticket outlining TODOs and known bugs can be found here: https://gem5.atlassian.net/browse/GEM5-648 Change-Id: I3492ec4a6d8c59ffbae899ce8e87ab4ffb92b976 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/47466 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
129 lines
5.0 KiB
Python
129 lines
5.0 KiB
Python
# Copyright (c) 2021 The Regents of the University of California
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from components_library.processors.simple_core import SimpleCore
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from components_library.processors.abstract_core import AbstractCore
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import m5
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from typing import Dict, Any, List
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from .abstract_processor import AbstractProcessor
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from ..boards.abstract_board import AbstractBoard
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from ..utils.override import *
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class SwitchableProcessor(AbstractProcessor):
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"""
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This class can be used to setup a switchable processor/processors on a
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system.
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Though this class can be used directly, it is best inherited from. See
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"SimpleSwitchableCPU" for an example of this.
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"""
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def __init__(
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self,
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switchable_cores: Dict[Any, List[SimpleCore]],
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starting_cores: Any,
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) -> None:
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if starting_cores not in switchable_cores.keys():
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raise AssertionError(
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f"Key {starting_cores} cannot be found in the "
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"switchable_processors dictionary."
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)
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self._current_cores = switchable_cores[starting_cores]
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self._switchable_cores = switchable_cores
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all_cores = []
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for core_list in self._switchable_cores.values():
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for core in core_list:
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core.set_switched_out(core not in self._current_cores)
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all_cores.append(core)
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super(SwitchableProcessor, self).__init__(cores=all_cores)
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@overrides(AbstractProcessor)
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def incorporate_processor(self, board: AbstractBoard) -> None:
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# This is a bit of a hack. The `m5.switchCpus` function, used in the
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# "switch_to_processor" function, requires the System simobject as an
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# argument. We therefore need to store the board when incorporating the
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# procsesor
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self._board = board
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@overrides(AbstractProcessor)
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def get_num_cores(self) -> int:
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# Note: This is a special case where the total number of cores in the
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# design is not the number of cores, due to some being switched out.
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return len(self._current_cores)
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@overrides(AbstractProcessor)
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def get_cores(self) -> List[AbstractCore]:
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return self._current_cores
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def switch_to_processor(self, switchable_core_key: Any):
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# Run various checks.
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if not hasattr(self, "_board"):
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raise AssertionError("The processor has not been incorporated.")
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if switchable_core_key not in self._switchable_cores.keys():
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raise AssertionError(
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f"Key {switchable_core_key} is not a key in the"
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" switchable_processor dictionary."
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)
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# Select the correct processor to switch to.
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to_switch = self._switchable_cores[switchable_core_key]
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# Run more checks.
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if to_switch == self._current_cores:
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raise AssertionError(
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"Cannot swap current cores with the current cores"
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)
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if len(to_switch) != len(self._current_cores):
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raise AssertionError(
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"The number of cores to swap in is not the same as the number "
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"already swapped in. This is not allowed."
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)
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current_core_simobj = [
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core.get_simobject() for core in self._current_cores
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]
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to_switch_simobj = [core.get_simobject() for core in to_switch]
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# Switch the CPUs
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m5.switchCpus(
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self._board,
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list(zip(current_core_simobj, to_switch_simobj)),
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)
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# Ensure the current processor is updated.
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self._current_cores = to_switch
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