6411b2255c
Introduce far atomic operations in CHI protocol.
Three configuration parameters have been used to tune this behavior:
policy_type: sets the atomic policy to one of the described in our paper
atomic_op_latency: simulates the AMO ALU operation latency
comp_anr: configures the Atomic No return transaction to split
CompDBIDResp into two different messages DBIDResp and Comp
Change-Id: I087afad9ad9fcb9df42d72893c9e32ad5a5eb478
882 lines
41 KiB
Plaintext
882 lines
41 KiB
Plaintext
/*
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* Copyright (c) 2021-2023 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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machine(MachineType:Cache, "Cache coherency protocol") :
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// Sequencer to insert Load/Store requests.
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// May be null if this is not a L1 cache
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Sequencer * sequencer;
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// Cache for storing local lines.
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// NOTE: it is assumed that a cache tag and directory lookups and updates
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// happen in parallel. The cache tag latency is used for both cases.
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CacheMemory * cache;
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// Additional pipeline latency modeling for the different request types
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// When defined, these are applied after the initial tag array read and
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// sending necessary snoops.
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Cycles read_hit_latency := 0;
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Cycles read_miss_latency := 0;
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Cycles atomic_op_latency := 0;
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Cycles write_fe_latency := 0; // Front-end: Rcv req -> Snd req
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Cycles write_be_latency := 0; // Back-end: Rcv ack -> Snd data
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Cycles fill_latency := 0; // Fill latency
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Cycles snp_latency := 0; // Applied before handling any snoop
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Cycles snp_inv_latency := 0; // Additional latency for invalidating snoops
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// Waits for cache data array write to complete before executing next action
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// Note a new write will always block if bank stalls are enabled in the cache
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bool wait_for_cache_wr := "False";
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// Request TBE allocation latency
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Cycles allocation_latency := 0;
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// Enqueue latencies for outgoing messages
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// NOTE: should remove this and only use parameters above?
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Cycles request_latency := 1;
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Cycles response_latency := 1;
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Cycles snoop_latency := 1;
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Cycles data_latency := 1;
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Cycles dvm_ext_tlbi_latency := 6;
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// When an SC fails, unique lines are locked to this controller for a period
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// proportional to the number of consecutive failed SC requests. See
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// the usage of sc_lock_multiplier and llscCheckMonitor for details
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int sc_lock_base_latency_cy := 4;
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int sc_lock_multiplier_inc := 4;
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int sc_lock_multiplier_decay := 1;
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int sc_lock_multiplier_max := 256;
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bool sc_lock_enabled;
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// Maximum number of outstanding transactions from a single requester
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Addr max_outstanding_transactions := 1024;
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// Recycle latency on resource stalls
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Cycles stall_recycle_lat := 1;
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// Notify the sequencer when a line is evicted. This should be set is the
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// sequencer is not null and handled LL/SC request types.
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bool send_evictions;
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// Number of entries in the snoop, replacement, and DVM TBE tables
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// notice the "number_of_TBEs" parameter is defined by AbstractController
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int number_of_snoop_TBEs;
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int number_of_repl_TBEs;
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int number_of_DVM_TBEs;
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int number_of_DVM_snoop_TBEs;
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// replacements use the same TBE slot as the request that triggered it
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// in this case the number_of_repl_TBEs parameter is ignored
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bool unify_repl_TBEs;
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// wait for the final tag update to complete before deallocating TBE and
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// going to final stable state
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bool dealloc_wait_for_tag := "False";
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// Width of the data channel. Data transfer are split in multiple messages
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// at the protocol level when this is less than the cache line size.
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int data_channel_size;
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// Set when this is used as the home node and point of coherency of the
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// system. Must be false for every other cache level.
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bool is_HN;
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// Enables direct memory transfers between SNs and RNs when the data is
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// not cache in the HN.
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bool enable_DMT;
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// Use ReadNoSnpSep instead of ReadNoSnp for DMT requests, which allows
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// the TBE to be deallocated at HNFs before the requester receives the data
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bool enable_DMT_early_dealloc := "False";
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// Enables direct cache transfers, i.e., use forwarding snoops whenever
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// possible.
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bool enable_DCT;
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// Atomic Operation Policy
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// All Near executes all Atomics at L1 (variable set to 0; default)
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// Unique Near executes Atomics at HNF for states I, SC, SD (set to 1)
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// Present Near execites all Atomics at L1 except when state is I (set to 2)
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int policy_type := 1;
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// Use separate Comp/DBIDResp responses for WriteUnique
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bool comp_wu := "False";
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// additional latency for the WU Comp response
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Cycles comp_wu_latency := 0;
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// Use separate Comp/DBIDResp responses for AtomicNoResponse
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bool comp_anr := "False";
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// additional latency for the ANR Comp response
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Cycles comp_anr_latency := 0;
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// Controls cache clusivity for different request types.
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// set all alloc_on* to false to completelly disable caching
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bool alloc_on_readshared;
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bool alloc_on_readunique;
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bool alloc_on_readonce;
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bool alloc_on_writeback;
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bool alloc_on_seq_acc;
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bool alloc_on_seq_line_write;
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bool alloc_on_atomic;
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// Controls if the clusivity is strict.
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bool dealloc_on_unique;
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bool dealloc_on_shared;
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bool dealloc_backinv_unique;
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bool dealloc_backinv_shared;
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// If the responder has the line in UC or UD state, propagate this state
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// on a ReadShared. Notice data won't be deallocated if dealloc_on_unique is
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// set
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bool fwd_unique_on_readshared := "False";
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// Allow receiving data in SD state.
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bool allow_SD;
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// stall new requests to destinations with a pending retry
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bool throttle_req_on_retry := "True";
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// Use prefetcher
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bool use_prefetcher, default="false";
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// Message Queues
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// Interface to the network
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// Note vnet_type is used by Garnet only. "response" type is assumed to
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// have data, so use it for data channels and "none" for the rest.
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// network="To" for outbound queue; network="From" for inbound
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// virtual networks: 0=request, 1=snoop, 2=response, 3=data
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MessageBuffer * reqOut, network="To", virtual_network="0", vnet_type="none";
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MessageBuffer * snpOut, network="To", virtual_network="1", vnet_type="none";
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MessageBuffer * rspOut, network="To", virtual_network="2", vnet_type="none";
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MessageBuffer * datOut, network="To", virtual_network="3", vnet_type="response";
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MessageBuffer * reqIn, network="From", virtual_network="0", vnet_type="none";
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MessageBuffer * snpIn, network="From", virtual_network="1", vnet_type="none";
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MessageBuffer * rspIn, network="From", virtual_network="2", vnet_type="none";
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MessageBuffer * datIn, network="From", virtual_network="3", vnet_type="response";
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// Mandatory queue for receiving requests from the sequencer
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MessageBuffer * mandatoryQueue;
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// Internal queue for trigger events
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MessageBuffer * triggerQueue;
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// Internal queue for retry trigger events
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MessageBuffer * retryTriggerQueue;
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// Internal queue for accepted requests
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MessageBuffer * reqRdy;
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// Internal queue for accepted snoops
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MessageBuffer * snpRdy;
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// Internal queue for eviction requests
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MessageBuffer * replTriggerQueue;
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// Prefetch queue for receiving prefetch requests from prefetcher
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MessageBuffer * prefetchQueue;
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// Requests that originated from a prefetch in a upstream cache are treated
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// as demand access in this cache. Notice the demand access stats are still
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// updated only on true demand requests.
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bool upstream_prefetch_trains_prefetcher := "False";
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{
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////////////////////////////////////////////////////////////////////////////
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// States
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////////////////////////////////////////////////////////////////////////////
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state_declaration(State, default="Cache_State_null") {
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// Stable states
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I, AccessPermission:Invalid, desc="Invalid / not present locally or upstream";
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// States when block is present in local cache only
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SC, AccessPermission:Read_Only, desc="Shared Clean";
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UC, AccessPermission:Read_Write, desc="Unique Clean";
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SD, AccessPermission:Read_Only, desc="Shared Dirty";
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UD, AccessPermission:Read_Write, desc="Unique Dirty";
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UD_T, AccessPermission:Read_Write, desc="UD with use timeout";
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// Invalid in local cache but present in upstream caches
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RU, AccessPermission:Invalid, desc="Upstream requester has line in UD/UC";
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RSC, AccessPermission:Invalid, desc="Upstream requester has line in SC";
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RSD, AccessPermission:Invalid, desc="Upstream requester has line in SD and maybe SC";
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RUSC, AccessPermission:Invalid, desc="RSC + this node stills has exclusive access";
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RUSD, AccessPermission:Invalid, desc="RSD + this node stills has exclusive access";
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// Both in local and upstream caches. In some cases local maybe stale
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SC_RSC, AccessPermission:Read_Only, desc="SC + RSC";
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SD_RSC, AccessPermission:Read_Only, desc="SD + RSC";
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SD_RSD, AccessPermission:Read_Only, desc="SD + RSD";
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UC_RSC, AccessPermission:Read_Write, desc="UC + RSC";
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UC_RU, AccessPermission:Invalid, desc="UC + RU";
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UD_RU, AccessPermission:Invalid, desc="UD + RU";
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UD_RSD, AccessPermission:Read_Write, desc="UD + RSD";
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UD_RSC, AccessPermission:Read_Write, desc="UD + RSC";
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// DVM states - use AccessPermission:Invalid because this prevents "functional reads"
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DvmTlbi_Unconfirmed, AccessPermission:Invalid, desc="DVM TLBI waiting for confirmation from MN";
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DvmSync_Unsent, AccessPermission:Invalid, desc="DVM Sync waiting for previous TLBIs to complete";
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DvmSync_Unconfirmed, AccessPermission:Invalid, desc="DVM Sync waiting for confirmation from MN";
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DvmTlbi_Waiting, AccessPermission:Invalid, desc="DVM TLBI confirmed by MN, waiting for completion";
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DvmSync_Waiting, AccessPermission:Invalid, desc="DVM Sync confirmed by MN, waiting for completion";
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DvmOp_Finished, AccessPermission:Invalid, desc="DVM operation that has completed, about to be deallocated";
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DvmExtTlbi_Partial, AccessPermission:Invalid, desc="External DVM TLBI waiting for second packet from MN";
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DvmExtTlbi_Executing, AccessPermission:Invalid, desc="External DVM TLBI being executed by this machine";
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DvmExtSync_Partial, AccessPermission:Invalid, desc="External DVM Sync waiting for second packet from MN";
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DvmExtSync_Executing, AccessPermission:Invalid, desc="External DVM Sync being executed by this machine";
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DvmExtOp_Finished, AccessPermission:Invalid, desc="External DVM operation that has completed, about to be deallocated";
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// Generic transient state
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// There is only a transient "BUSY" state. The actions taken at this state
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// and the final stable state are defined by information in the TBE.
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// While on BUSY_INTR, we will reply to incoming snoops and the
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// state of the cache line may change. While on BUSY_BLKD snoops
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// are blocked
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BUSY_INTR, AccessPermission:Busy, desc="Waiting for data and/or ack";
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BUSY_BLKD, AccessPermission:Busy, desc="Waiting for data and/or ack; blocks snoops";
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// Null state for debugging
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null, AccessPermission:Invalid, desc="Null state";
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}
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////////////////////////////////////////////////////////////////////////////
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// Events
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////////////////////////////////////////////////////////////////////////////
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enumeration(Event) {
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// Events triggered by incoming requests. Allocate TBE and move
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// request or snoop to the ready queue
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AllocRequest, desc="Allocates a TBE for a request. Triggers a retry if table is full";
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AllocRequestWithCredit, desc="Allocates a TBE for a request. Always succeeds.";
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AllocSeqRequest, desc="Allocates a TBE for a sequencer request. Stalls requests if table is full";
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AllocSeqDvmRequest, desc="Allocates a TBE for a sequencer DVM request. Stalls requests if table is full";
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AllocPfRequest, desc="Allocates a TBE for a prefetch request. Stalls requests if table is full";
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AllocSnoop, desc="Allocates a TBE for a snoop. Stalls snoop if table is full";
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AllocDvmSnoop, desc="Allocated a TBE for a DVM snoop. Stalls snoop if table is full";
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// Events triggered by sequencer requests or snoops in the rdy queue
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// See CHIRequestType in CHi-msg.sm for descriptions
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Load, desc="", in_trans="yes";
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Store, desc="", in_trans="yes";
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AtomicLoad, desc="", in_trans="yes";
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AtomicStore, desc="", in_trans="yes";
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Prefetch, desc="", in_trans="yes";
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ReadShared, desc="", in_trans="yes";
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ReadNotSharedDirty, desc="", in_trans="yes";
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ReadUnique, desc="", in_trans="yes";
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ReadUnique_PoC, desc="", in_trans="yes";
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ReadOnce, desc="", in_trans="yes";
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CleanUnique, desc="", in_trans="yes";
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Evict, desc="", in_trans="yes";
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WriteBackFull, desc="", in_trans="yes";
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WriteEvictFull, desc="", in_trans="yes";
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WriteCleanFull, desc="", in_trans="yes";
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WriteUnique, desc="", in_trans="yes";
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WriteUniquePtl_PoC, desc="", in_trans="yes";
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WriteUniqueFull_PoC, desc="", in_trans="yes";
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WriteUniqueFull_PoC_Alloc, desc="", in_trans="yes";
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AtomicReturn, desc="", in_trans="yes";
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AtomicNoReturn, desc="", in_trans="yes";
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AtomicReturn_PoC, desc="", in_trans="yes";
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AtomicNoReturn_PoC, desc="", in_trans="yes";
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SnpCleanInvalid, desc="", in_trans="yes";
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SnpShared, desc="", in_trans="yes";
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SnpSharedFwd, desc="", in_trans="yes";
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SnpNotSharedDirtyFwd, desc="", in_trans="yes";
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SnpUnique, desc="", in_trans="yes";
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SnpUniqueFwd, desc="", in_trans="yes";
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SnpOnce, desc="", in_trans="yes";
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SnpOnceFwd, desc="", in_trans="yes";
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SnpStalled, desc="", in_trans="yes"; // A snoop stall triggered from the inport
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// DVM sequencer requests
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DvmTlbi_Initiate, desc="", out_trans="yes", in_trans="yes"; // triggered when a CPU core wants to send a TLBI
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// TLBIs are handled entirely within Ruby, so there's no ExternCompleted message
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DvmSync_Initiate, desc="", out_trans="yes", in_trans="yes"; // triggered when a CPU core wants to send a sync
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DvmSync_ExternCompleted, desc=""; // triggered when an externally requested Sync is completed
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// Events triggered by incoming response messages
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// See CHIResponseType in CHi-msg.sm for descriptions
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CompAck, desc="";
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Comp_I, desc="";
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Comp_UC, desc="";
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Comp_SC, desc="";
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CompDBIDResp, desc="";
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DBIDResp, desc="";
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Comp, desc="";
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ReadReceipt, desc="";
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RespSepData, desc="";
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SnpResp_I, desc="";
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SnpResp_I_Fwded_UC, desc="";
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SnpResp_I_Fwded_UD_PD, desc="";
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SnpResp_SC, desc="";
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SnpResp_SC_Fwded_SC, desc="";
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SnpResp_SC_Fwded_SD_PD, desc="";
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SnpResp_UC_Fwded_I, desc="";
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SnpResp_UD_Fwded_I, desc="";
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SnpResp_SC_Fwded_I, desc="";
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SnpResp_SD_Fwded_I, desc="";
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RetryAck, desc="";
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RetryAck_PoC, desc="";
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PCrdGrant, desc="";
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PCrdGrant_PoC, desc="";
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RetryAck_Hazard, desc="";
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RetryAck_PoC_Hazard, desc="";
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PCrdGrant_Hazard, desc="";
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PCrdGrant_PoC_Hazard, desc="";
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// Events triggered by incoming DVM messages
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SnpDvmOpSync_P1, desc="", in_trans="yes";
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SnpDvmOpSync_P2, desc="", in_trans="yes";
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SnpDvmOpNonSync_P1, desc="", in_trans="yes";
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SnpDvmOpNonSync_P2, desc="", in_trans="yes";
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// Events triggered by incoming data response messages
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// See CHIDataType in CHi-msg.sm for descriptions
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CompData_I, desc="";
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CompData_UC, desc="";
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CompData_SC, desc="";
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CompData_UD_PD, desc="";
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CompData_SD_PD, desc="";
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DataSepResp_UC, desc="";
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CBWrData_I, desc="";
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CBWrData_UC, desc="";
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CBWrData_SC, desc="";
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CBWrData_UD_PD, desc="";
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CBWrData_SD_PD, desc="";
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NCBWrData, desc="";
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SnpRespData_I, desc="";
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SnpRespData_I_PD, desc="";
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SnpRespData_SC, desc="";
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SnpRespData_SC_PD, desc="";
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SnpRespData_SD, desc="";
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SnpRespData_UC, desc="";
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SnpRespData_UD, desc="";
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SnpRespData_SC_Fwded_SC, desc="";
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SnpRespData_SC_Fwded_SD_PD, desc="";
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SnpRespData_SC_PD_Fwded_SC, desc="";
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SnpRespData_I_Fwded_SD_PD, desc="";
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SnpRespData_I_PD_Fwded_SC, desc="";
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SnpRespData_I_Fwded_SC, desc="";
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// We use special events for requests that we detect to be stale. This is
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// done for debugging only. We sent a stale response so the requester can
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// confirm the request is indeed stale and this is not a protocol bug.
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// A Write or Evict becomes stale when the requester receives a snoop that
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// changes the state of the data while the request was pending.
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// Actual CHI implementations don't have this check.
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Evict_Stale, desc="", in_trans="yes";
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WriteBackFull_Stale, desc="", in_trans="yes";
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WriteEvictFull_Stale, desc="", in_trans="yes";
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WriteCleanFull_Stale, desc="", in_trans="yes";
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CleanUnique_Stale, desc="", in_trans="yes";
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// Cache fill handling
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CheckCacheFill, desc="Check if need to write or update the cache and trigger any necessary allocation and evictions";
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// Internal requests generated to evict or writeback a local copy
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// to free-up cache space
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Local_Eviction, in_trans="yes", desc="Evicts/WB the local copy of the line";
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LocalHN_Eviction, in_trans="yes", desc="Local_Eviction triggered when is HN";
|
|
Global_Eviction, in_trans="yes", desc="Local_Eviction + back-invalidate line in all upstream requesters";
|
|
|
|
// Events triggered from tbe.actions
|
|
// In general, for each event we define a single transition from
|
|
// BUSY_BLKD and/or BUSY_INTR.
|
|
// See processNextState functions and Initiate_* actions.
|
|
// All triggered transitions execute in the same cycle until it has to wait
|
|
// for pending pending responses or data (set by expected_req_resp and
|
|
// expected_snp_resp). Triggers queued with pushNB are executed even if
|
|
// there are pending messages.
|
|
|
|
// Cache/directory access events. Notice these only model the latency.
|
|
TagArrayRead, desc="Read the cache and directory tag array";
|
|
TagArrayWrite, desc="Write the cache and directory tag array";
|
|
DataArrayRead, desc="Read the cache data array";
|
|
DataArrayWrite, desc="Write the cache data array";
|
|
DataArrayWriteOnFill, desc="Write the cache data array (cache fill)";
|
|
|
|
// Events for modeling the pipeline latency
|
|
ReadHitPipe, desc="Latency of reads served from local cache";
|
|
ReadMissPipe, desc="Latency of reads not served from local cache";
|
|
WriteFEPipe, desc="Front-end latency of write requests";
|
|
WriteBEPipe, desc="Back-end latency of write requests";
|
|
FillPipe, desc="Cache fill latency";
|
|
DelayAtomic, desc="Atomic operation latency";
|
|
SnpSharedPipe, desc="Latency for SnpShared requests";
|
|
SnpInvPipe, desc="Latency for SnpUnique and SnpCleanInv requests";
|
|
SnpOncePipe, desc="Latency for SnpOnce requests";
|
|
|
|
// Send a read request downstream.
|
|
SendReadShared, out_trans="yes", desc="Send a ReadShared or ReadNotSharedDirty is allow_SD is false";
|
|
SendReadOnce, out_trans="yes", desc="Send a ReadOnce";
|
|
SendReadNoSnp, out_trans="yes", desc="Send a SendReadNoSnp";
|
|
SendReadNoSnpDMT, out_trans="yes", desc="Send a SendReadNoSnp using DMT";
|
|
SendReadUnique, out_trans="yes", desc="Send a ReadUnique";
|
|
SendCompAck, desc="Send CompAck";
|
|
// Read handling at the completer
|
|
SendCompData, desc="Send CompData";
|
|
WaitCompAck, desc="Expect to receive CompAck";
|
|
SendRespSepData, desc="Send RespSepData for a DMT request";
|
|
|
|
// Send a write request downstream.
|
|
SendWriteBackOrWriteEvict, out_trans="yes", desc="Send a WriteBackFull (if line is UD or SD) or WriteEvictFull (if UC)";
|
|
SendWriteClean, out_trans="yes", desc="Send a WriteCleanFull";
|
|
SendWriteNoSnp, out_trans="yes", desc="Send a WriteNoSnp for a full line";
|
|
SendWriteNoSnpPartial, out_trans="yes", desc="Send a WriteNoSnpPtl";
|
|
SendWriteUnique, out_trans="yes", desc="Send a WriteUniquePtl";
|
|
SendWBData, desc="Send writeback data";
|
|
SendWUData, desc="Send write unique data";
|
|
SendWUDataCB, desc="Send write unique data from a sequencer callback";
|
|
// Write handling at the completer
|
|
SendCompDBIDResp, desc="Ack WB with CompDBIDResp";
|
|
SendCompDBIDRespStale, desc="Ack stale WB with CompDBIDResp";
|
|
SendCompDBIDResp_WU, desc="Ack WU with CompDBIDResp and set expected data";
|
|
SendDBIDResp_WU, desc="Ack WU with DBIDResp and set expected data";
|
|
SendComp_WU, desc="Ack WU completion";
|
|
|
|
// Send an atomic request downstream.
|
|
SendAtomicReturn, out_trans="yes", desc="Send atomic request with return";
|
|
SendAtomicReturn_NoWait, out_trans="yes", desc="Send atomic request with return, but no DBID";
|
|
SendAtomicNoReturn, out_trans="yes", desc="Send atomic request without return";
|
|
SendARData, desc="Send atomic return request data";
|
|
SendANRData, desc="Send atomic no return request data";
|
|
// Atomic handling at the completer
|
|
SendDBIDResp_AR, desc="Ack AR with DBIDResp and set expected data";
|
|
SendCompData_AR, desc="Ack AR completion";
|
|
SendCompDBIDResp_ANR, desc="Ack ANR with CompDBIDResp and set expected data";
|
|
SendDBIDResp_ANR, desc="Ack ANR with DBIDResp and set expected data";
|
|
SendComp_ANR, desc="Ack ANR completion";
|
|
|
|
|
|
// Dataless requests
|
|
SendEvict, out_trans="yes", desc="Send a Evict";
|
|
SendCompIResp, desc="Ack Evict with Comp_I";
|
|
SendCleanUnique,out_trans="yes", desc="Send a CleanUnique";
|
|
SendCompUCResp, desc="Ack CleanUnique with Comp_UC";
|
|
SendCompUCRespStale, desc="Ack stale CleanUnique with Comp_UC";
|
|
|
|
// Checks if an upgrade using a CleanUnique was sucessfull
|
|
CheckUpgrade_FromStore, desc="Upgrade needed by a Store";
|
|
CheckUpgrade_FromCU, desc="Upgrade needed by an upstream CleanUnique";
|
|
CheckUpgrade_FromRU, desc="Upgrade needed by an upstream ReadUnique";
|
|
|
|
// Snoop requests
|
|
// SnpNotSharedDirty are sent instead of SnpShared for ReadNotSharedDirty
|
|
SendSnpShared, desc="Send a SnpShared/SnpNotSharedDirty to sharer in UC,UD, or SD state";
|
|
SendSnpSharedFwdToOwner, desc="Send a SnpSharedFwd/SnpNotSharedDirtyFwd to sharer in UC,UD, or SD state";
|
|
SendSnpSharedFwdToSharer, desc="Send a SnpSharedFwd/SnpNotSharedDirtyFwd to a sharer in SC state";
|
|
SendSnpOnce, desc="Send a SnpOnce to a sharer";
|
|
SendSnpOnceFwd, desc="Send a SnpOnceFwd to a sharer";
|
|
SendSnpUnique, desc="Send a SnpUnique to all sharers";
|
|
SendSnpUniqueRetToSrc, desc="Send a SnpUnique to all sharers. Sets RetToSrc for only one sharer.";
|
|
SendSnpUniqueFwd, desc="Send a SnpUniqueFwd to a single sharer";
|
|
SendSnpCleanInvalid, desc="Send a SnpCleanInvalid to all sharers";
|
|
SendSnpCleanInvalidNoReq, desc="Send a SnpCleanInvalid to all sharers except requestor";
|
|
// Snoop responses
|
|
SendSnpData, desc="Send SnpRespData as snoop reply";
|
|
SendSnpIResp, desc="Send SnpResp_I as snoop reply";
|
|
SendInvSnpResp, desc="Check data state and queue either SendSnpIResp or SendSnpData";
|
|
SendSnpUniqueFwdCompData, desc="Send CompData to SnpUniqueFwd target and queue either SendSnpFwdedData or SendSnpFwdedResp";
|
|
SendSnpSharedFwdCompData, desc="Send CompData to SnpUniqueFwd target and queue either SendSnpFwdedData or SendSnpFwdedResp";
|
|
SendSnpNotSharedDirtyFwdCompData, desc="Send CompData to SnpNotSharedDirtyFwd target and queue either SendSnpFwdedData or SendSnpFwdedResp";
|
|
SendSnpOnceFwdCompData, desc="Send CompData to SnpOnceFwd target and queue either SendSnpFwdedData or SendSnpFwdedResp";
|
|
SendSnpFwdedData, desc="Send SnpResp for a forwarding snoop";
|
|
SendSnpFwdedResp, desc="Send SnpRespData for a forwarding snoop";
|
|
|
|
// DVM sends
|
|
DvmSync_Send, desc="Send an unstarted DVM Sync";
|
|
|
|
// Retry handling
|
|
SendRetryAck, desc="Send RetryAck";
|
|
SendPCrdGrant, desc="Send PCrdGrant";
|
|
DoRetry, desc="Resend the current pending request";
|
|
DoRetry_Hazard, desc="DoRetry during a hazard";
|
|
|
|
// Misc triggers
|
|
LoadHit, desc="Complete a load hit";
|
|
StoreHit, desc="Complete a store hit";
|
|
AtomicHit, desc="Complete an atomic hit";
|
|
UseTimeout, desc="Transition from UD_T -> UD";
|
|
RestoreFromHazard, desc="Restore from a snoop hazard";
|
|
TX_Data, desc="Transmit pending data messages";
|
|
MaintainCoherence, desc="Queues a WriteBack or Evict before droping the only valid copy of the block";
|
|
FinishCleanUnique, desc="Sends acks and perform any writeback after a CleanUnique";
|
|
FinishCopyBack_Stale, desc="Check if a Evict needs to be sent";
|
|
ActionStalledOnHazard, desc="Stall a trigger action because until finish handling snoop hazard";
|
|
|
|
// This is triggered once a transaction doesn't have
|
|
// any queued action and is not expecting responses/data. The transaction
|
|
// is finalized and the next stable state is stored in the cache/directory
|
|
// See the processNextState and makeFinalState functions
|
|
Final, desc="";
|
|
|
|
null, desc="";
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////////
|
|
// Data structures
|
|
////////////////////////////////////////////////////////////////////////////
|
|
|
|
// Cache block size
|
|
int blockSize, default="RubySystem::getBlockSizeBytes()";
|
|
|
|
// CacheEntry
|
|
structure(CacheEntry, interface="AbstractCacheEntry") {
|
|
State state, desc="SLICC line state";
|
|
DataBlock DataBlk, desc="data for the block";
|
|
bool HWPrefetched, default="false", desc="Set if this cache entry was prefetched";
|
|
}
|
|
|
|
// Directory entry
|
|
structure(DirEntry, interface="AbstractCacheEntry", main="false") {
|
|
NetDest sharers, desc="All upstream controllers that have this line (includes ownwer)";
|
|
MachineID owner, desc="Controller that has the line in UD,UC, or SD state";
|
|
bool ownerExists, default="false", desc="true if owner exists";
|
|
bool ownerIsExcl, default="false", desc="true if owner is UD or UC";
|
|
State state, desc="SLICC line state";
|
|
}
|
|
|
|
// Helper class for tracking expected response and data messages
|
|
structure(ExpectedMap, external ="yes") {
|
|
void clear(int dataChunks);
|
|
void addExpectedRespType(CHIResponseType);
|
|
void addExpectedDataType(CHIDataType);
|
|
void setExpectedCount(int val);
|
|
void addExpectedCount(int val);
|
|
bool hasExpected();
|
|
bool hasReceivedResp();
|
|
bool hasReceivedData();
|
|
int expected();
|
|
int received();
|
|
bool receiveResp(CHIResponseType);
|
|
bool receiveData(CHIDataType);
|
|
bool receivedDataType(CHIDataType);
|
|
bool receivedRespType(CHIResponseType);
|
|
}
|
|
|
|
// Tracks a pending retry
|
|
structure(RetryQueueEntry) {
|
|
Addr addr, desc="Line address";
|
|
bool usesTxnId, desc="Uses a transaction ID instead of a memory address";
|
|
MachineID retryDest, desc="Retry destination";
|
|
}
|
|
|
|
// Queue for event triggers. Used to specify a list of actions that need
|
|
// to be performed across multiple transitions.
|
|
// This class is also used to track pending retries
|
|
structure(TriggerQueue, external ="yes") {
|
|
Event front();
|
|
Event back();
|
|
bool frontNB();
|
|
bool backNB();
|
|
bool empty();
|
|
void push(Event);
|
|
void pushNB(Event);
|
|
void pushFront(Event);
|
|
void pushFrontNB(Event);
|
|
void pop();
|
|
// For the retry queue
|
|
void emplace(Addr,bool,MachineID);
|
|
RetryQueueEntry next(); //SLICC won't allow to reuse front()
|
|
}
|
|
|
|
// TBE fields
|
|
structure(TBE, desc="Transaction buffer entry definition") {
|
|
// in which table was this allocated
|
|
bool is_req_tbe, desc="Allocated in the request table";
|
|
bool is_snp_tbe, desc="Allocated in the snoop table";
|
|
bool is_repl_tbe, desc="Allocated in the replacements table";
|
|
bool is_dvm_tbe, desc="Allocated in the DVM table";
|
|
bool is_dvm_snp_tbe, desc="Allocated in the DVM snoop table";
|
|
|
|
int storSlot, desc="Slot in the storage tracker occupied by this entry";
|
|
|
|
// Transaction info mostly extracted from the request message
|
|
Addr addr, desc="Line address for this TBE";
|
|
Addr accAddr, desc="Access address for Load/Store/WriteUniquePtl; otherwisse == addr";
|
|
int accSize, desc="Access size for Load/Store/WriteUniquePtl; otherwisse == blockSize";
|
|
CHIRequestType reqType, desc="Request type that initiated this transaction";
|
|
Addr txnId, desc="Transaction ID. We default to -1 for debug purposes", default="-1";
|
|
MachineID requestor, desc="Requestor ID";
|
|
MachineID fwdRequestor, desc="Requestor to receive data on fwding snoops";
|
|
bool use_DMT, desc="Use DMT for this transaction";
|
|
bool use_DCT, desc="Use DCT for this transaction";
|
|
|
|
// if either is set prefetchers are not notified on miss/hit/fill and
|
|
// demand hit/miss stats are not incremented
|
|
bool is_local_pf, desc="Request generated by a local prefetcher";
|
|
bool is_remote_pf, desc="Request generated a prefetcher in another cache";
|
|
|
|
// Atomic info associated with the transaction
|
|
WriteMask atomic_op, desc="Atomic Operation Wrapper";
|
|
bool atomic_to_be_done, desc="We have yet to perform the atomic";
|
|
|
|
// NOTE: seqReq is a smart pointer pointing to original CPU request object
|
|
// that triggers transactions associated with this TBE. seqReq carries some
|
|
// information (e.g., PC of requesting instruction, virtual address of this
|
|
// request, etc.). Not all transactions have this field set if they are not
|
|
// triggered directly by a demand request from CPU.
|
|
RequestPtr seqReq, default="nullptr", desc="Pointer to original request from CPU/sequencer";
|
|
bool isSeqReqValid, default="false", desc="Set if seqReq is valid (not nullptr)";
|
|
|
|
// Transaction state information
|
|
State state, desc="SLICC line state";
|
|
|
|
// Transient state information. These are set at the beggining of a
|
|
// transactions and updated as data and responses are received. After
|
|
// finalizing the transactions these are used to create the next SLICC
|
|
// stable state.
|
|
bool hasUseTimeout, desc="Line is locked under store/use timeout";
|
|
DataBlock dataBlk, desc="Local copy of the line";
|
|
DataBlock oldDataBlk, desc="Local copy of the line before executing atomic";
|
|
WriteMask dataBlkValid, desc="Marks which bytes in the DataBlock are valid";
|
|
bool dataValid, desc="Local copy is valid";
|
|
bool dataAMOValid, desc="Local copy is valid for AMO";
|
|
bool dataDirty, desc="Local copy is dirtry";
|
|
bool dataMaybeDirtyUpstream, desc="Line maybe dirty upstream";
|
|
bool dataUnique, desc="Line is unique either locally or upsatream";
|
|
bool dataToBeInvalid, desc="Local copy will be invalidated at the end of transaction";
|
|
bool dataToBeSharedClean, desc="Local copy will become SC at the end of transaction";
|
|
NetDest dir_sharers, desc="Upstream controllers that have the line (includes owner)";
|
|
MachineID dir_owner, desc="Owner ID";
|
|
bool dir_ownerExists, desc="Owner ID is valid";
|
|
bool dir_ownerIsExcl, desc="Owner is UD or UC; SD otherwise";
|
|
bool doCacheFill, desc="Write valid data to the cache when completing transaction";
|
|
// NOTE: dataMaybeDirtyUpstream and dir_ownerExists are the same except
|
|
// when we had just sent dirty data upstream and are waiting for ack to set
|
|
// dir_ownerExists
|
|
|
|
// Helper structures to track expected events and additional transient
|
|
// state info
|
|
|
|
// List of actions to be performed while on a transient state
|
|
// See the processNextState function for details
|
|
TriggerQueue actions, template="<Cache_Event>", desc="List of actions";
|
|
Event pendAction, desc="Current pending action";
|
|
Tick delayNextAction, desc="Delay next action until given tick";
|
|
State finalState, desc="Final state; set when pendAction==Final";
|
|
|
|
// List of expected responses and data. Checks the type of data against the
|
|
// expected ones for debugging purposes
|
|
// See the processNextState function for details
|
|
ExpectedMap expected_req_resp, template="<CHIResponseType,CHIDataType>";
|
|
ExpectedMap expected_snp_resp, template="<CHIResponseType,CHIDataType>";
|
|
bool defer_expected_comp; // expect to receive Comp before the end of transaction
|
|
CHIResponseType slicchack1; // fix compiler not including headers
|
|
CHIDataType slicchack2; // fix compiler not including headers
|
|
|
|
// Tracks pending data messages that need to be generated when sending
|
|
// a line
|
|
bool snd_pendEv, desc="Is there a pending tx event ?";
|
|
WriteMask snd_pendBytes, desc="Which bytes are pending transmission";
|
|
CHIDataType snd_msgType, desc="Type of message being sent";
|
|
MachineID snd_destination, desc="Data destination";
|
|
|
|
// Tracks how to update the directory when receiving a CompAck
|
|
bool updateDirOnCompAck, desc="Update directory on CompAck";
|
|
bool requestorToBeOwner, desc="Sets dir_ownerExists";
|
|
bool requestorToBeExclusiveOwner, desc="Sets dir_ownerIsExcl";
|
|
// NOTE: requestor always added to dir_sharers if updateDirOnCompAck is set
|
|
|
|
// Set for incoming snoop requests
|
|
bool snpNeedsData, desc="Set if snoop requires data as response";
|
|
State fwdedState, desc="State of CompData sent due to a forwarding snoop";
|
|
bool is_req_hazard, desc="Snoop hazard with an outstanding request";
|
|
bool is_repl_hazard, desc="Snoop hazard with an outstanding writeback request";
|
|
bool is_stale, desc="Request is now stale because of a snoop hazard";
|
|
|
|
// Tracks requests sent downstream
|
|
CHIRequestType pendReqType, desc="Sent request type";
|
|
bool pendReqAllowRetry, desc="Sent request can be retried";
|
|
bool rcvdRetryAck, desc="Received a RetryAck";
|
|
bool rcvdRetryCredit, desc="Received a PCrdGrant";
|
|
// NOTE: the message is retried only after receiving both RetryAck and
|
|
// PCrdGrant. A request can be retried only once.
|
|
// These are a copy of the retry msg fields in case we need to retry
|
|
Addr pendReqAccAddr;
|
|
int pendReqAccSize;
|
|
NetDest pendReqDest;
|
|
bool pendReqD2OrigReq;
|
|
bool pendReqRetToSrc;
|
|
|
|
// This TBE stalled a message and thus we need to call wakeUpBuffers
|
|
// at some point
|
|
bool wakeup_pending_req;
|
|
bool wakeup_pending_snp;
|
|
bool wakeup_pending_tgr;
|
|
}
|
|
|
|
// TBE table definition
|
|
structure(TBETable, external ="yes") {
|
|
TBE lookup(Addr);
|
|
void allocate(Addr);
|
|
void deallocate(Addr);
|
|
bool isPresent(Addr);
|
|
}
|
|
|
|
structure(TBEStorage, external ="yes") {
|
|
int size();
|
|
int capacity();
|
|
int reserved();
|
|
int slotsAvailable();
|
|
bool areNSlotsAvailable(int n);
|
|
void incrementReserved();
|
|
void decrementReserved();
|
|
int addEntryToNewSlot();
|
|
void addEntryToSlot(int slot);
|
|
void removeEntryFromSlot(int slot);
|
|
}
|
|
|
|
// Directory memory definition
|
|
structure(PerfectCacheMemory, external = "yes") {
|
|
void allocate(Addr);
|
|
void deallocate(Addr);
|
|
DirEntry lookup(Addr);
|
|
bool isTagPresent(Addr);
|
|
}
|
|
|
|
// Directory
|
|
PerfectCacheMemory directory, template="<Cache_DirEntry>";
|
|
|
|
// Tracks unique lines locked after a store miss
|
|
TimerTable useTimerTable;
|
|
|
|
// Multiplies sc_lock_base_latency to obtain the lock timeout.
|
|
// This is incremented at Profile_Eviction and decays on
|
|
// store miss completion
|
|
int sc_lock_multiplier, default="0";
|
|
|
|
// Definitions of the TBE tables
|
|
|
|
// Main TBE table used for incoming requests
|
|
TBETable TBEs, template="<Cache_TBE>", constructor="m_number_of_TBEs";
|
|
TBEStorage storTBEs, constructor="this, m_number_of_TBEs";
|
|
|
|
// TBE table for WriteBack/Evict requests generated by a replacement
|
|
// Notice storTBEs will be used when unify_repl_TBEs is set
|
|
TBETable replTBEs, template="<Cache_TBE>", constructor="m_unify_repl_TBEs ? m_number_of_TBEs : m_number_of_repl_TBEs";
|
|
TBEStorage storReplTBEs, constructor="this, m_number_of_repl_TBEs";
|
|
|
|
// TBE table for incoming snoops
|
|
TBETable snpTBEs, template="<Cache_TBE>", constructor="m_number_of_snoop_TBEs";
|
|
TBEStorage storSnpTBEs, constructor="this, m_number_of_snoop_TBEs";
|
|
|
|
// TBE table for outgoing DVM requests
|
|
TBETable dvmTBEs, template="<Cache_TBE>", constructor="m_number_of_DVM_TBEs";
|
|
TBEStorage storDvmTBEs, constructor="this, m_number_of_DVM_TBEs";
|
|
|
|
// TBE table for incoming DVM snoops
|
|
TBETable dvmSnpTBEs, template="<Cache_TBE>", constructor="m_number_of_DVM_snoop_TBEs";
|
|
TBEStorage storDvmSnpTBEs, constructor="this, m_number_of_DVM_snoop_TBEs";
|
|
|
|
// DVM data
|
|
// Queue of non-sync operations that haven't been Comp-d yet.
|
|
// Before a Sync operation can start, this queue must be emptied
|
|
TriggerQueue dvmPendingNonSyncsBlockingSync, template="<Cache_Event>";
|
|
// Used to record if a Sync op is pending
|
|
bool dvmHasPendingSyncOp, default="false";
|
|
Addr dvmPendingSyncOp, default="0";
|
|
|
|
// Retry handling
|
|
|
|
// Destinations that will be sent PCrdGrant when a TBE becomes available
|
|
TriggerQueue retryQueue, template="<Cache_RetryQueueEntry>";
|
|
|
|
|
|
// Pending RetryAck/PCrdGrant/DoRetry
|
|
structure(RetryTriggerMsg, interface="Message") {
|
|
Addr addr;
|
|
Event event;
|
|
MachineID retryDest;
|
|
bool usesTxnId;
|
|
Addr txnId;
|
|
|
|
bool functionalRead(Packet *pkt) { return false; }
|
|
bool functionalRead(Packet *pkt, WriteMask &mask) { return false; }
|
|
bool functionalWrite(Packet *pkt) { return false; }
|
|
}
|
|
|
|
// Destinations from we received a RetryAck. Sending new requests to these
|
|
// destinations will be blocked until a PCrdGrant is received if
|
|
// throttle_req_on_retry is set
|
|
NetDest destsWaitingRetry;
|
|
|
|
// Pending transaction actions (generated by TBE:actions)
|
|
structure(TriggerMsg, interface="Message") {
|
|
Addr addr;
|
|
bool usesTxnId;
|
|
bool from_hazard; // this actions was generate during a snoop hazard
|
|
bool functionalRead(Packet *pkt) { return false; }
|
|
bool functionalRead(Packet *pkt, WriteMask &mask) { return false; }
|
|
bool functionalWrite(Packet *pkt) { return false; }
|
|
}
|
|
|
|
// Internal replacement request
|
|
structure(ReplacementMsg, interface="Message") {
|
|
Addr addr;
|
|
Addr from_addr;
|
|
int slot; // set only when unify_repl_TBEs is set
|
|
bool functionalRead(Packet *pkt) { return false; }
|
|
bool functionalRead(Packet *pkt, WriteMask &mask) { return false; }
|
|
bool functionalWrite(Packet *pkt) { return false; }
|
|
}
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////
|
|
// Input/output port definitions
|
|
////////////////////////////////////////////////////////////////////////////
|
|
|
|
include "CHI-cache-ports.sm";
|
|
// CHI-cache-ports.sm also includes CHI-cache-funcs.sm
|
|
|
|
////////////////////////////////////////////////////////////////////////////
|
|
// Actions and transitions
|
|
////////////////////////////////////////////////////////////////////////////
|
|
|
|
include "CHI-cache-actions.sm";
|
|
include "CHI-cache-transitions.sm";
|
|
}
|