The event in KVM x86 SE mode plays double duty, triggering a system call or a page fault depending on where it's called from (the system call handler vs page fault handler). This means we can eliminate the page fault gem5 op and the pseudo_inst.hh switching header file. This change touches a lot of things, but there wasn't really a good place to split it up which still made sense and was consistent and functional. Change-Id: Ic414829917bcbd421893aa6c89d78273e4926b78 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34165 Reviewed-by: Gabe Black <gabe.black@gmail.com> Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
225 lines
7.9 KiB
Python
225 lines
7.9 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2016-2017 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import sys
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import os
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import re
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from gem5_scons import Transform
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Import('*')
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#################################################################
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#
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# ISA "switch header" generation.
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#
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# Auto-generate arch headers that include the right ISA-specific
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# header based on the setting of THE_ISA preprocessor variable.
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#
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#################################################################
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env.SwitchingHeaders(
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Split('''
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decoder.hh
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isa.hh
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isa_traits.hh
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locked_mem.hh
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registers.hh
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remote_gdb.hh
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types.hh
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utility.hh
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'''),
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env.subst('${TARGET_ISA}'))
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if env['BUILD_GPU']:
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env.SwitchingHeaders(
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Split('''
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gpu_decoder.hh
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gpu_isa.hh
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gpu_types.hh
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'''),
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env.subst('${TARGET_GPU_ISA}'))
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#################################################################
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#
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# Include architecture-specific files.
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#
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#################################################################
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#
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# Build a SCons scanner for ISA files
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#
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import SCons.Scanner
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import SCons.Tool
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scanner = SCons.Scanner.Classic("ISAScan",
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[".isa", ".ISA"],
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"SRCDIR",
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r'^\s*##include\s+"([\w/.-]*)"')
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env.Append(SCANNERS=scanner)
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# Tell scons that when it sees a cc.inc file, it should scan it for includes.
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SCons.Tool.SourceFileScanner.add_scanner('.cc.inc', SCons.Tool.CScanner)
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#
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# Now create a Builder object that uses isa_parser.py to generate C++
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# output from the ISA description (*.isa) files.
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#
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parser_files = Glob('isa_parser/*.py')
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micro_asm_py = File('micro_asm.py')
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# import ply here because SCons screws with sys.path when performing actions.
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import ply
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arch_dir = Dir('.')
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def run_parser(target, source, env):
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# Add the current directory to the system path so we can import files.
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sys.path[0:0] = [ arch_dir.abspath ]
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import isa_parser
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parser = isa_parser.ISAParser(target[0].dir.abspath)
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parser.parse_isa_desc(source[0].abspath)
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desc_action = MakeAction(run_parser, Transform("ISA DESC", 1))
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IsaDescBuilder = Builder(action=desc_action)
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# ISAs should use this function to set up an IsaDescBuilder and not try to
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# set one up manually.
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def ISADesc(desc, decoder_splits=1, exec_splits=1):
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'''Set up a builder for an ISA description.
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The decoder_splits and exec_splits parameters let us determine what
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files the isa parser is actually going to generate. This needs to match
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what files are actually generated, and there's no specific check for that
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right now.
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If the parser itself is responsible for generating a list of its products
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and their dependencies, then using that output to set up the right
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dependencies. This is what we used to do. The problem is that scons
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fundamentally doesn't support using a build product to affect its graph
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of possible products, dependencies, builders, etc. There are a couple ways
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to work around that limitation.
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One option is to compute dependencies while the build phase of scons is
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running. That method can be quite complicated and cumbersome, because we
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have to make sure our modifications are made before scons tries to
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consume them. There's also no guarantee that this mechanism will work since
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it subverts scons expectations and changes things behind its back. This
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was implemented previously and constrained the builds parallelism
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significantly.
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Another option would be to recursively call scons to have it update the
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list of products/dependencies during the setup phase of this invocation of
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scons. The problem with that is that it would be very difficult to make
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the sub-invocation of scons observe the options passed to the primary one
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in all possible cases, or to even determine conclusively what the name of
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the scons executable is in the first place.
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Possible future changes to the isa parser might make it easier to
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determine what files it would generate, perhaps because there was a more
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direct correspondence between input files and output files. Or, if the
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parser could run quickly and determine what its output files would be
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without having do actually generate those files, then it could be run
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unconditionally without slowing down all builds or touching the output
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files unnecessarily.
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'''
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generated_dir = File(desc).dir.up().Dir('generated')
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def gen_file(name):
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return generated_dir.File(name)
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gen = []
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def add_gen(name):
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gen.append(gen_file(name))
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# Tell scons about the various files the ISA parser will generate.
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add_gen('decoder-g.cc.inc')
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add_gen('decoder-ns.cc.inc')
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add_gen('decode-method.cc.inc')
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add_gen('decoder.hh')
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add_gen('decoder-g.hh.inc')
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add_gen('decoder-ns.hh.inc')
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add_gen('exec-g.cc.inc')
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add_gen('exec-ns.cc.inc')
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add_gen('max_inst_regs.hh')
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# These generated files are also top level sources.
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def source_gen(name):
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add_gen(name)
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Source(gen_file(name))
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source_gen('decoder.cc')
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if decoder_splits == 1:
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source_gen('inst-constrs.cc')
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else:
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for i in range(1, decoder_splits + 1):
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source_gen('inst-constrs-%d.cc' % i)
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if exec_splits == 1:
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source_gen('generic_cpu_exec.cc')
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else:
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for i in range(1, exec_splits + 1):
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source_gen('generic_cpu_exec_%d.cc' % i)
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# Actually create the builder.
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sources = [desc, micro_asm_py] + parser_files
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IsaDescBuilder(target=gen, source=sources, env=env)
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return gen
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Export('ISADesc')
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DebugFlag('IntRegs')
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DebugFlag('FloatRegs')
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DebugFlag('VecRegs')
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DebugFlag('VecPredRegs')
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DebugFlag('CCRegs')
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DebugFlag('MiscRegs')
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CompoundFlag('Registers', [ 'IntRegs', 'FloatRegs', 'VecRegs', 'VecPredRegs',
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'CCRegs', 'MiscRegs' ])
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