gem5/src/cpu/o3 at 63371c86648ed65a453a95aec80f326f15a9666d - gem5

base_dyn_inst.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

bpred_unit_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

bpred_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

bpred_unit.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

checker_builder.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

comm.hh

O3: Cleanup the commitInfo comm struct.

2011-03-17 19:20:19 -05:00

commit_impl.hh

stats: rename stats so they can be used as python expressions

2011-04-19 18:45:21 -07:00

commit.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

commit.hh

includes: fix up code after sorting

2011-04-15 10:44:14 -07:00

cpu_builder.cc

o3-smt: enforce numThreads parameter for SMT SE mode

2009-07-25 00:50:27 -04:00

cpu_policy.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

cpu.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

cpu.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

decode_impl.hh

stats: rename stats so they can be used as python expressions

2011-04-19 18:45:21 -07:00

decode.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

decode.hh

Move sched_list.hh and timebuf.hh from src/base to src/cpu.

2011-01-03 14:35:47 -08:00

dep_graph.hh

ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.

2010-10-31 00:07:20 -07:00

dyn_inst_impl.hh

O3: Make all instructions that write a misc. register not perform the write until commit.

2010-12-07 16:19:57 -08:00

dyn_inst.cc

O3: Generaize the O3 IMPL class so it isn't split out by ISA.

2008-10-09 00:10:02 -07:00

dyn_inst.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

fetch_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

fetch.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

fetch.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

free_list.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

free_list.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

fu_pool.cc

params: Deprecate old-style constructors; update most SimObject constructors.

2007-08-30 15:16:59 -04:00

fu_pool.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

FuncUnitConfig.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

FUPool.py

CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

2010-11-15 14:04:04 -06:00

iew_impl.hh

stats: rename stats so they can be used as python expressions

2011-04-19 18:45:21 -07:00

iew.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

iew.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

impl.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue_impl.hh

stats: rename stats so they can be used as python expressions

2011-04-19 18:45:21 -07:00

inst_queue.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

inst_queue.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

isa_specific.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

lsq_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

lsq_unit_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

lsq_unit.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq_unit.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

lsq.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

lsq.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

mem_dep_unit_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

mem_dep_unit.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

mem_dep_unit.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

O3Checker.py

python: Move more code into m5.util allow SCons to use that code.

2009-09-22 15:24:16 -07:00

O3CPU.py

O3: Tighten memory order violation checking to 16 bytes.

2011-04-04 11:42:23 -05:00

regfile.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

rename_impl.hh

stats: rename stats so they can be used as python expressions

2011-04-19 18:45:21 -07:00

rename_map.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

rename_map.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

rename.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rename.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

rob_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

rob.cc

now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu/o3/alpha directory

2006-06-30 20:49:31 -04:00

rob.hh

includes: fix up code after sorting

2011-04-15 10:44:14 -07:00

sat_counter.cc

Merge ktlim@zizzer:/bk/newmem

2006-06-02 18:19:50 -04:00

sat_counter.hh

types: Move stuff for global types into src/base/types.hh

2009-05-17 14:34:50 -07:00

SConscript

inorder-o3: allow both to compile together

2009-05-12 15:01:14 -04:00

SConsopts

cpu_models: get rid of cpu_models.py and move the stuff into SCons

2010-02-26 18:14:48 -08:00

scoreboard.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

scoreboard.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

store_set.cc

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

store_set.hh

types: add a type for thread IDs and try to use it everywhere

2009-05-26 09:23:13 -07:00

thread_context_impl.hh

trace: reimplement the DTRACE function so it doesn't use a vector

2011-04-15 10:44:32 -07:00

thread_context.cc

includes: sort all includes

2011-04-15 10:44:06 -07:00

thread_context.hh

includes: sort all includes

2011-04-15 10:44:06 -07:00

thread_state.hh

Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.

2009-07-08 23:02:22 -07:00