62ae85c0a2
Recent Linux kernels for AArch64 have changed their start addresses but we still want to relocate the kernel to 0x80080000 which required hacking the load_addr_mask in Realview.py to be 0x7ffffff from 0xfffffff to mask off the proper number of MSBs to load the kernel in the desired location. To avoid having to make this change in the future again, we auto-calculate the load_addr_mask if it is specified as 0x0 in the System sim-object to find the most restrictive address mask instead of having the configuration specify it. If the configuration does specify the address mask, we use it instead of auto-calculating. Change-Id: I18aabb5d09945c6e3e3819c9c8036ea24b6c35cf Signed-off-by: Geoffrey Blake <Geoffrey.Blake@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2323 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
942 lines
37 KiB
Python
942 lines
37 KiB
Python
# Copyright (c) 2009-2017 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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# Gabe Black
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# William Wang
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from m5.params import *
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from m5.proxy import *
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from ClockDomain import ClockDomain
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from VoltageDomain import VoltageDomain
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from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
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from PciHost import *
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from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
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from Ide import *
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from Platform import Platform
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from Terminal import Terminal
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from Uart import Uart
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from SimpleMemory import SimpleMemory
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from Gic import *
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from EnergyCtrl import EnergyCtrl
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from ClockDomain import SrcClockDomain
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from SubSystem import SubSystem
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from Graphics import ImageFormat
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# Platforms with KVM support should generally use in-kernel GIC
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# emulation. Use a GIC model that automatically switches between
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# gem5's GIC model and KVM's GIC model if KVM is available.
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try:
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from KvmGic import MuxingKvmGic
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kvm_gicv2_class = MuxingKvmGic
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except ImportError:
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# KVM support wasn't compiled into gem5. Fallback to a
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# software-only GIC.
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kvm_gicv2_class = Pl390
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pass
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class AmbaPioDevice(BasicPioDevice):
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type = 'AmbaPioDevice'
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abstract = True
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cxx_header = "dev/arm/amba_device.hh"
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amba_id = Param.UInt32("ID of AMBA device for kernel detection")
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class AmbaIntDevice(AmbaPioDevice):
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type = 'AmbaIntDevice'
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abstract = True
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cxx_header = "dev/arm/amba_device.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrupt number that connects to GIC")
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int_delay = Param.Latency("100ns",
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"Time between action and interrupt generation by device")
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class AmbaDmaDevice(DmaDevice):
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type = 'AmbaDmaDevice'
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abstract = True
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cxx_header = "dev/arm/amba_device.hh"
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pio_addr = Param.Addr("Address for AMBA slave interface")
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pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device")
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrupt number that connects to GIC")
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amba_id = Param.UInt32("ID of AMBA device for kernel detection")
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class A9SCU(BasicPioDevice):
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type = 'A9SCU'
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cxx_header = "dev/arm/a9scu.hh"
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class ArmPciIntRouting(Enum): vals = [
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'ARM_PCI_INT_STATIC',
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'ARM_PCI_INT_DEV',
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'ARM_PCI_INT_PIN',
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]
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class GenericArmPciHost(GenericPciHost):
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type = 'GenericArmPciHost'
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cxx_header = "dev/arm/pci_host.hh"
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int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy")
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int_base = Param.Unsigned("PCI interrupt base")
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int_count = Param.Unsigned("Maximum number of interrupts used by this host")
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class RealViewCtrl(BasicPioDevice):
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type = 'RealViewCtrl'
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cxx_header = "dev/arm/rv_ctrl.hh"
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proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID")
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proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1")
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idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID")
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class RealViewOsc(ClockDomain):
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type = 'RealViewOsc'
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cxx_header = "dev/arm/rv_ctrl.hh"
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parent = Param.RealViewCtrl(Parent.any, "RealView controller")
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# TODO: We currently don't have the notion of a clock source,
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# which means we have to associate oscillators with a voltage
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# source.
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voltage_domain = Param.VoltageDomain(Parent.voltage_domain,
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"Voltage domain")
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# See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
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# the individual core/logic tile reference manuals for details
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# about the site/position/dcc/device allocation.
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site = Param.UInt8("Board Site")
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position = Param.UInt8("Position in device stack")
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dcc = Param.UInt8("Daughterboard Configuration Controller")
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device = Param.UInt8("Device ID")
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freq = Param.Clock("Default frequency")
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class RealViewTemperatureSensor(SimObject):
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type = 'RealViewTemperatureSensor'
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cxx_header = "dev/arm/rv_ctrl.hh"
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parent = Param.RealViewCtrl(Parent.any, "RealView controller")
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system = Param.System(Parent.any, "system")
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# See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and
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# the individual core/logic tile reference manuals for details
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# about the site/position/dcc/device allocation.
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site = Param.UInt8("Board Site")
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position = Param.UInt8("Position in device stack")
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dcc = Param.UInt8("Daughterboard Configuration Controller")
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device = Param.UInt8("Device ID")
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class VExpressMCC(SubSystem):
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"""ARM V2M-P1 Motherboard Configuration Controller
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This subsystem describes a subset of the devices that sit behind the
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motherboard configuration controller on the the ARM Motherboard
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Express (V2M-P1) motherboard. See ARM DUI 0447J for details.
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"""
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class Osc(RealViewOsc):
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site, position, dcc = (0, 0, 0)
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class Temperature(RealViewTemperatureSensor):
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site, position, dcc = (0, 0, 0)
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osc_mcc = Osc(device=0, freq="50MHz")
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osc_clcd = Osc(device=1, freq="23.75MHz")
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osc_peripheral = Osc(device=2, freq="24MHz")
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osc_system_bus = Osc(device=4, freq="24MHz")
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# See Table 4.19 in ARM DUI 0447J (Motherboard Express uATX TRM).
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temp_crtl = Temperature(device=0)
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class CoreTile2A15DCC(SubSystem):
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"""ARM CoreTile Express A15x2 Daughterboard Configuration Controller
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This subsystem describes a subset of the devices that sit behind the
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daughterboard configuration controller on a CoreTile Express A15x2. See
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ARM DUI 0604E for details.
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"""
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class Osc(RealViewOsc):
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site, position, dcc = (1, 0, 0)
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# See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM)
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osc_cpu = Osc(device=0, freq="60MHz")
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osc_hsbm = Osc(device=4, freq="40MHz")
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osc_pxl = Osc(device=5, freq="23.75MHz")
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osc_smb = Osc(device=6, freq="50MHz")
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osc_sys = Osc(device=7, freq="60MHz")
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osc_ddr = Osc(device=8, freq="40MHz")
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class VGic(PioDevice):
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type = 'VGic'
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cxx_header = "dev/arm/vgic.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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platform = Param.Platform(Parent.any, "Platform this device is part of.")
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vcpu_addr = Param.Addr(0, "Address for vcpu interfaces")
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hv_addr = Param.Addr(0, "Address for hv control")
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pio_delay = Param.Latency('10ns', "Delay for PIO r/w")
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# The number of list registers is not currently configurable at runtime.
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ppint = Param.UInt32("HV maintenance interrupt number")
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class AmbaFake(AmbaPioDevice):
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type = 'AmbaFake'
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cxx_header = "dev/arm/amba_fake.hh"
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ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)")
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amba_id = 0;
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class Pl011(Uart):
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type = 'Pl011'
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cxx_header = "dev/arm/pl011.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrupt number that connects to GIC")
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end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART")
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int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART")
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class Sp804(AmbaPioDevice):
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type = 'Sp804'
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cxx_header = "dev/arm/timer_sp804.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num0 = Param.UInt32("Interrupt number that connects to GIC")
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clock0 = Param.Clock('1MHz', "Clock speed of the input")
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int_num1 = Param.UInt32("Interrupt number that connects to GIC")
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clock1 = Param.Clock('1MHz', "Clock speed of the input")
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amba_id = 0x00141804
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class A9GlobalTimer(BasicPioDevice):
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type = 'A9GlobalTimer'
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cxx_header = "dev/arm/timer_a9global.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num = Param.UInt32("Interrrupt number that connects to GIC")
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class CpuLocalTimer(BasicPioDevice):
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type = 'CpuLocalTimer'
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cxx_header = "dev/arm/timer_cpulocal.hh"
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gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
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int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
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int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
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class GenericTimer(SimObject):
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type = 'GenericTimer'
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cxx_header = "dev/arm/generic_timer.hh"
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system = Param.ArmSystem(Parent.any, "system")
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gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
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# @todo: for now only two timers per CPU is supported, which is the
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# normal behaviour when security extensions are disabled.
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int_phys = Param.UInt32("Physical timer interrupt number")
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int_virt = Param.UInt32("Virtual timer interrupt number")
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class GenericTimerMem(PioDevice):
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type = 'GenericTimerMem'
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cxx_header = "dev/arm/generic_timer.hh"
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gic = Param.BaseGic(Parent.any, "GIC to use for interrupting")
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base = Param.Addr(0, "Base address")
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int_phys = Param.UInt32("Interrupt number")
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int_virt = Param.UInt32("Interrupt number")
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class PL031(AmbaIntDevice):
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type = 'PL031'
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cxx_header = "dev/arm/rtc_pl031.hh"
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time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)")
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amba_id = 0x00341031
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class Pl050(AmbaIntDevice):
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type = 'Pl050'
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cxx_header = "dev/arm/kmi.hh"
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vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
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is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard")
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int_delay = '1us'
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amba_id = 0x00141050
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class Pl111(AmbaDmaDevice):
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type = 'Pl111'
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cxx_header = "dev/arm/pl111.hh"
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pixel_clock = Param.Clock('24MHz', "Pixel clock")
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vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display")
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amba_id = 0x00141111
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enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
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class HDLcd(AmbaDmaDevice):
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type = 'HDLcd'
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cxx_header = "dev/arm/hdlcd.hh"
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vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer "
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"display")
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amba_id = 0x00141000
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workaround_swap_rb = Param.Bool(False, "Workaround incorrect color "
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"selector order in some kernels")
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workaround_dma_line_count = Param.Bool(True, "Workaround incorrect "
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"DMA line count (off by 1)")
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enable_capture = Param.Bool(True, "capture frame to "
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"system.framebuffer.{extension}")
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frame_format = Param.ImageFormat("Auto",
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"image format of the captured frame")
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pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range")
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pxl_clk = Param.ClockDomain("Pixel clock source")
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pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch")
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virt_refresh_rate = Param.Frequency("20Hz", "Frame refresh rate "
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"in KVM mode")
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class RealView(Platform):
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type = 'RealView'
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cxx_header = "dev/arm/realview.hh"
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system = Param.System(Parent.any, "system")
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_mem_regions = [(Addr(0), Addr('256MB'))]
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def _on_chip_devices(self):
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return []
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def _off_chip_devices(self):
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return []
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_off_chip_ranges = []
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def _attach_device(self, device, bus, dma_ports=None):
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if hasattr(device, "pio"):
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device.pio = bus.master
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if hasattr(device, "dma"):
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if dma_ports is None:
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device.dma = bus.slave
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else:
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dma_ports.append(device.dma)
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def _attach_io(self, devices, *args, **kwargs):
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for d in devices:
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self._attach_device(d, *args, **kwargs)
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def _attach_clk(self, devices, clkdomain):
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for d in devices:
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if hasattr(d, "clk_domain"):
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d.clk_domain = clkdomain
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def attachPciDevices(self):
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pass
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def enableMSIX(self):
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pass
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def onChipIOClkDomain(self, clkdomain):
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self._attach_clk(self._on_chip_devices(), clkdomain)
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def offChipIOClkDomain(self, clkdomain):
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self._attach_clk(self._off_chip_devices(), clkdomain)
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def attachOnChipIO(self, bus, bridge=None, *args, **kwargs):
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self._attach_io(self._on_chip_devices(), bus, *args, **kwargs)
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if bridge:
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bridge.ranges = self._off_chip_ranges
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def attachIO(self, *args, **kwargs):
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self._attach_io(self._off_chip_devices(), *args, **kwargs)
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def setupBootLoader(self, mem_bus, cur_sys, loc):
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self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'),
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conf_table_reported = False)
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self.nvmem.port = mem_bus.master
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cur_sys.boot_loader = loc('boot.arm')
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cur_sys.atags_addr = 0x100
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cur_sys.load_offset = 0
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# Reference for memory map and interrupt number
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# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A)
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# Chapter 4: Programmer's Reference
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class RealViewPBX(RealView):
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uart = Pl011(pio_addr=0x10009000, int_num=44)
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realview_io = RealViewCtrl(pio_addr=0x10000000)
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mcc = VExpressMCC()
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dcc = CoreTile2A15DCC()
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gic = Pl390()
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pci_host = GenericPciHost(
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conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
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pci_pio_base=0)
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timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
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timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
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global_timer = A9GlobalTimer(int_num=27, pio_addr=0x1f000200)
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local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
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pio_addr=0x1f000600)
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clcd = Pl111(pio_addr=0x10020000, int_num=55)
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kmi0 = Pl050(pio_addr=0x10006000, int_num=52)
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kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True)
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a9scu = A9SCU(pio_addr=0x1f000000)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2,
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io_shift = 1, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0x18000000, BAR0Size = '16B',
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BAR1 = 0x18000100, BAR1Size = '1B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)
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flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000,
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fake_mem=True)
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dmac_fake = AmbaFake(pio_addr=0x10030000)
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uart1_fake = AmbaFake(pio_addr=0x1000a000)
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uart2_fake = AmbaFake(pio_addr=0x1000b000)
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uart3_fake = AmbaFake(pio_addr=0x1000c000)
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smc_fake = AmbaFake(pio_addr=0x100e1000)
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sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
|
|
watchdog_fake = AmbaFake(pio_addr=0x10010000)
|
|
gpio0_fake = AmbaFake(pio_addr=0x10013000)
|
|
gpio1_fake = AmbaFake(pio_addr=0x10014000)
|
|
gpio2_fake = AmbaFake(pio_addr=0x10015000)
|
|
ssp_fake = AmbaFake(pio_addr=0x1000d000)
|
|
sci_fake = AmbaFake(pio_addr=0x1000e000)
|
|
aaci_fake = AmbaFake(pio_addr=0x10004000)
|
|
mmc_fake = AmbaFake(pio_addr=0x10005000)
|
|
rtc = PL031(pio_addr=0x10017000, int_num=42)
|
|
energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
|
|
|
|
|
|
# Attach I/O devices that are on chip and also set the appropriate
|
|
# ranges for the bridge
|
|
def attachOnChipIO(self, bus, bridge):
|
|
self.gic.pio = bus.master
|
|
self.l2x0_fake.pio = bus.master
|
|
self.a9scu.pio = bus.master
|
|
self.global_timer.pio = bus.master
|
|
self.local_cpu_timer.pio = bus.master
|
|
# Bridge ranges based on excluding what is part of on-chip I/O
|
|
# (gic, l2x0, a9scu, local_cpu_timer)
|
|
bridge.ranges = [AddrRange(self.realview_io.pio_addr,
|
|
self.a9scu.pio_addr - 1),
|
|
AddrRange(self.flash_fake.pio_addr,
|
|
self.flash_fake.pio_addr + \
|
|
self.flash_fake.pio_size - 1)]
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "close" to the cores.
|
|
def onChipIOClkDomain(self, clkdomain):
|
|
self.gic.clk_domain = clkdomain
|
|
self.l2x0_fake.clk_domain = clkdomain
|
|
self.a9scu.clkdomain = clkdomain
|
|
self.local_cpu_timer.clk_domain = clkdomain
|
|
|
|
# Attach I/O devices to specified bus object. Can't do this
|
|
# earlier, since the bus object itself is typically defined at the
|
|
# System level.
|
|
def attachIO(self, bus):
|
|
self.uart.pio = bus.master
|
|
self.realview_io.pio = bus.master
|
|
self.pci_host.pio = bus.master
|
|
self.timer0.pio = bus.master
|
|
self.timer1.pio = bus.master
|
|
self.clcd.pio = bus.master
|
|
self.clcd.dma = bus.slave
|
|
self.kmi0.pio = bus.master
|
|
self.kmi1.pio = bus.master
|
|
self.cf_ctrl.pio = bus.master
|
|
self.cf_ctrl.dma = bus.slave
|
|
self.dmac_fake.pio = bus.master
|
|
self.uart1_fake.pio = bus.master
|
|
self.uart2_fake.pio = bus.master
|
|
self.uart3_fake.pio = bus.master
|
|
self.smc_fake.pio = bus.master
|
|
self.sp810_fake.pio = bus.master
|
|
self.watchdog_fake.pio = bus.master
|
|
self.gpio0_fake.pio = bus.master
|
|
self.gpio1_fake.pio = bus.master
|
|
self.gpio2_fake.pio = bus.master
|
|
self.ssp_fake.pio = bus.master
|
|
self.sci_fake.pio = bus.master
|
|
self.aaci_fake.pio = bus.master
|
|
self.mmc_fake.pio = bus.master
|
|
self.rtc.pio = bus.master
|
|
self.flash_fake.pio = bus.master
|
|
self.energy_ctrl.pio = bus.master
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "far" away from the cores.
|
|
def offChipIOClkDomain(self, clkdomain):
|
|
self.uart.clk_domain = clkdomain
|
|
self.realview_io.clk_domain = clkdomain
|
|
self.timer0.clk_domain = clkdomain
|
|
self.timer1.clk_domain = clkdomain
|
|
self.clcd.clk_domain = clkdomain
|
|
self.kmi0.clk_domain = clkdomain
|
|
self.kmi1.clk_domain = clkdomain
|
|
self.cf_ctrl.clk_domain = clkdomain
|
|
self.dmac_fake.clk_domain = clkdomain
|
|
self.uart1_fake.clk_domain = clkdomain
|
|
self.uart2_fake.clk_domain = clkdomain
|
|
self.uart3_fake.clk_domain = clkdomain
|
|
self.smc_fake.clk_domain = clkdomain
|
|
self.sp810_fake.clk_domain = clkdomain
|
|
self.watchdog_fake.clk_domain = clkdomain
|
|
self.gpio0_fake.clk_domain = clkdomain
|
|
self.gpio1_fake.clk_domain = clkdomain
|
|
self.gpio2_fake.clk_domain = clkdomain
|
|
self.ssp_fake.clk_domain = clkdomain
|
|
self.sci_fake.clk_domain = clkdomain
|
|
self.aaci_fake.clk_domain = clkdomain
|
|
self.mmc_fake.clk_domain = clkdomain
|
|
self.rtc.clk_domain = clkdomain
|
|
self.flash_fake.clk_domain = clkdomain
|
|
self.energy_ctrl.clk_domain = clkdomain
|
|
|
|
# Reference for memory map and interrupt number
|
|
# RealView Emulation Baseboard User Guide (ARM DUI 0143B)
|
|
# Chapter 4: Programmer's Reference
|
|
class RealViewEB(RealView):
|
|
uart = Pl011(pio_addr=0x10009000, int_num=44)
|
|
realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500)
|
|
mcc = VExpressMCC()
|
|
dcc = CoreTile2A15DCC()
|
|
gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000)
|
|
timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
|
|
timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
|
|
clcd = Pl111(pio_addr=0x10020000, int_num=23)
|
|
kmi0 = Pl050(pio_addr=0x10006000, int_num=20)
|
|
kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True)
|
|
|
|
l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
|
|
flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1,
|
|
fake_mem=True)
|
|
dmac_fake = AmbaFake(pio_addr=0x10030000)
|
|
uart1_fake = AmbaFake(pio_addr=0x1000a000)
|
|
uart2_fake = AmbaFake(pio_addr=0x1000b000)
|
|
uart3_fake = AmbaFake(pio_addr=0x1000c000)
|
|
smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1)
|
|
smc_fake = AmbaFake(pio_addr=0x100e1000)
|
|
sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True)
|
|
watchdog_fake = AmbaFake(pio_addr=0x10010000)
|
|
gpio0_fake = AmbaFake(pio_addr=0x10013000)
|
|
gpio1_fake = AmbaFake(pio_addr=0x10014000)
|
|
gpio2_fake = AmbaFake(pio_addr=0x10015000)
|
|
ssp_fake = AmbaFake(pio_addr=0x1000d000)
|
|
sci_fake = AmbaFake(pio_addr=0x1000e000)
|
|
aaci_fake = AmbaFake(pio_addr=0x10004000)
|
|
mmc_fake = AmbaFake(pio_addr=0x10005000)
|
|
rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031)
|
|
energy_ctrl = EnergyCtrl(pio_addr=0x1000f000)
|
|
|
|
# Attach I/O devices that are on chip and also set the appropriate
|
|
# ranges for the bridge
|
|
def attachOnChipIO(self, bus, bridge):
|
|
self.gic.pio = bus.master
|
|
self.l2x0_fake.pio = bus.master
|
|
# Bridge ranges based on excluding what is part of on-chip I/O
|
|
# (gic, l2x0)
|
|
bridge.ranges = [AddrRange(self.realview_io.pio_addr,
|
|
self.gic.cpu_addr - 1),
|
|
AddrRange(self.flash_fake.pio_addr, Addr.max)]
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "close" to the cores.
|
|
def onChipIOClkDomain(self, clkdomain):
|
|
self.gic.clk_domain = clkdomain
|
|
self.l2x0_fake.clk_domain = clkdomain
|
|
|
|
# Attach I/O devices to specified bus object. Can't do this
|
|
# earlier, since the bus object itself is typically defined at the
|
|
# System level.
|
|
def attachIO(self, bus):
|
|
self.uart.pio = bus.master
|
|
self.realview_io.pio = bus.master
|
|
self.pci_host.pio = bus.master
|
|
self.timer0.pio = bus.master
|
|
self.timer1.pio = bus.master
|
|
self.clcd.pio = bus.master
|
|
self.clcd.dma = bus.slave
|
|
self.kmi0.pio = bus.master
|
|
self.kmi1.pio = bus.master
|
|
self.dmac_fake.pio = bus.master
|
|
self.uart1_fake.pio = bus.master
|
|
self.uart2_fake.pio = bus.master
|
|
self.uart3_fake.pio = bus.master
|
|
self.smc_fake.pio = bus.master
|
|
self.sp810_fake.pio = bus.master
|
|
self.watchdog_fake.pio = bus.master
|
|
self.gpio0_fake.pio = bus.master
|
|
self.gpio1_fake.pio = bus.master
|
|
self.gpio2_fake.pio = bus.master
|
|
self.ssp_fake.pio = bus.master
|
|
self.sci_fake.pio = bus.master
|
|
self.aaci_fake.pio = bus.master
|
|
self.mmc_fake.pio = bus.master
|
|
self.rtc_fake.pio = bus.master
|
|
self.flash_fake.pio = bus.master
|
|
self.smcreg_fake.pio = bus.master
|
|
self.energy_ctrl.pio = bus.master
|
|
|
|
# Set the clock domain for IO objects that are considered
|
|
# to be "far" away from the cores.
|
|
def offChipIOClkDomain(self, clkdomain):
|
|
self.uart.clk_domain = clkdomain
|
|
self.realview_io.clk_domain = clkdomain
|
|
self.timer0.clk_domain = clkdomain
|
|
self.timer1.clk_domain = clkdomain
|
|
self.clcd.clk_domain = clkdomain
|
|
self.kmi0.clk_domain = clkdomain
|
|
self.kmi1.clk_domain = clkdomain
|
|
self.dmac_fake.clk_domain = clkdomain
|
|
self.uart1_fake.clk_domain = clkdomain
|
|
self.uart2_fake.clk_domain = clkdomain
|
|
self.uart3_fake.clk_domain = clkdomain
|
|
self.smc_fake.clk_domain = clkdomain
|
|
self.sp810_fake.clk_domain = clkdomain
|
|
self.watchdog_fake.clk_domain = clkdomain
|
|
self.gpio0_fake.clk_domain = clkdomain
|
|
self.gpio1_fake.clk_domain = clkdomain
|
|
self.gpio2_fake.clk_domain = clkdomain
|
|
self.ssp_fake.clk_domain = clkdomain
|
|
self.sci_fake.clk_domain = clkdomain
|
|
self.aaci_fake.clk_domain = clkdomain
|
|
self.mmc_fake.clk_domain = clkdomain
|
|
self.rtc.clk_domain = clkdomain
|
|
self.flash_fake.clk_domain = clkdomain
|
|
self.smcreg_fake.clk_domain = clkdomain
|
|
self.energy_ctrl.clk_domain = clkdomain
|
|
|
|
class VExpress_EMM(RealView):
|
|
_mem_regions = [(Addr('2GB'), Addr('2GB'))]
|
|
|
|
# Ranges based on excluding what is part of on-chip I/O (gic,
|
|
# a9scu)
|
|
_off_chip_ranges = [AddrRange(0x2F000000, size='16MB'),
|
|
AddrRange(0x30000000, size='256MB'),
|
|
AddrRange(0x40000000, size='512MB'),
|
|
AddrRange(0x18000000, size='64MB'),
|
|
AddrRange(0x1C000000, size='64MB')]
|
|
|
|
# Platform control device (off-chip)
|
|
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
|
|
idreg=0x02250000, pio_addr=0x1C010000)
|
|
|
|
mcc = VExpressMCC()
|
|
dcc = CoreTile2A15DCC()
|
|
|
|
### On-chip devices ###
|
|
gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000)
|
|
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
|
|
|
|
local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30,
|
|
pio_addr=0x2C080000)
|
|
|
|
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
|
|
pio_addr=0x2b000000, int_num=117,
|
|
workaround_swap_rb=True)
|
|
|
|
def _on_chip_devices(self):
|
|
devices = [
|
|
self.gic, self.vgic,
|
|
self.local_cpu_timer
|
|
]
|
|
if hasattr(self, "gicv2m"):
|
|
devices.append(self.gicv2m)
|
|
devices.append(self.hdlcd)
|
|
return devices
|
|
|
|
### Off-chip devices ###
|
|
uart = Pl011(pio_addr=0x1c090000, int_num=37)
|
|
pci_host = GenericPciHost(
|
|
conf_base=0x30000000, conf_size='256MB', conf_device_bits=16,
|
|
pci_pio_base=0)
|
|
|
|
generic_timer = GenericTimer(int_phys=29, int_virt=27)
|
|
timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz')
|
|
timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz')
|
|
clcd = Pl111(pio_addr=0x1c1f0000, int_num=46)
|
|
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
|
|
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
|
|
cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
|
|
io_shift = 2, ctrl_offset = 2, Command = 0x1,
|
|
BAR0 = 0x1C1A0000, BAR0Size = '256B',
|
|
BAR1 = 0x1C1A0100, BAR1Size = '4096B',
|
|
BAR0LegacyIO = True, BAR1LegacyIO = True)
|
|
|
|
vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
|
|
conf_table_reported = False)
|
|
rtc = PL031(pio_addr=0x1C170000, int_num=36)
|
|
|
|
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
|
|
uart1_fake = AmbaFake(pio_addr=0x1C0A0000)
|
|
uart2_fake = AmbaFake(pio_addr=0x1C0B0000)
|
|
uart3_fake = AmbaFake(pio_addr=0x1C0C0000)
|
|
sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True)
|
|
watchdog_fake = AmbaFake(pio_addr=0x1C0F0000)
|
|
aaci_fake = AmbaFake(pio_addr=0x1C040000)
|
|
lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff)
|
|
usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff)
|
|
mmc_fake = AmbaFake(pio_addr=0x1c050000)
|
|
energy_ctrl = EnergyCtrl(pio_addr=0x1c080000)
|
|
|
|
def _off_chip_devices(self):
|
|
devices = [
|
|
self.uart,
|
|
self.realview_io,
|
|
self.pci_host,
|
|
self.timer0,
|
|
self.timer1,
|
|
self.clcd,
|
|
self.kmi0,
|
|
self.kmi1,
|
|
self.cf_ctrl,
|
|
self.rtc,
|
|
self.vram,
|
|
self.l2x0_fake,
|
|
self.uart1_fake,
|
|
self.uart2_fake,
|
|
self.uart3_fake,
|
|
self.sp810_fake,
|
|
self.watchdog_fake,
|
|
self.aaci_fake,
|
|
self.lan_fake,
|
|
self.usb_fake,
|
|
self.mmc_fake,
|
|
self.energy_ctrl,
|
|
]
|
|
# Try to attach the I/O if it exists
|
|
if hasattr(self, "ide"):
|
|
devices.append(self.ide)
|
|
if hasattr(self, "ethernet"):
|
|
devices.append(self.ethernet)
|
|
return devices
|
|
|
|
# Attach any PCI devices that are supported
|
|
def attachPciDevices(self):
|
|
self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
|
|
InterruptLine=1, InterruptPin=1)
|
|
self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
|
|
InterruptLine=2, InterruptPin=2)
|
|
|
|
def enableMSIX(self):
|
|
self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512)
|
|
self.gicv2m = Gicv2m()
|
|
self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)]
|
|
|
|
def setupBootLoader(self, mem_bus, cur_sys, loc):
|
|
self.nvmem = SimpleMemory(range = AddrRange('64MB'),
|
|
conf_table_reported = False)
|
|
self.nvmem.port = mem_bus.master
|
|
if not cur_sys.boot_loader:
|
|
cur_sys.boot_loader = loc('boot_emm.arm')
|
|
cur_sys.atags_addr = 0x8000000
|
|
cur_sys.load_offset = 0x80000000
|
|
|
|
class VExpress_EMM64(VExpress_EMM):
|
|
# Three memory regions are specified totalling 512GB
|
|
_mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')),
|
|
(Addr('512GB'), Addr('480GB'))]
|
|
pci_host = GenericPciHost(
|
|
conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
|
|
pci_pio_base=0x2f000000)
|
|
|
|
def setupBootLoader(self, mem_bus, cur_sys, loc):
|
|
self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
|
|
conf_table_reported=False)
|
|
self.nvmem.port = mem_bus.master
|
|
if not cur_sys.boot_loader:
|
|
cur_sys.boot_loader = loc('boot_emm.arm64')
|
|
cur_sys.atags_addr = 0x8000000
|
|
cur_sys.load_offset = 0x80000000
|
|
|
|
|
|
class VExpress_GEM5_V1(RealView):
|
|
"""
|
|
The VExpress gem5 memory map is loosely based on a modified
|
|
Versatile Express RS1 memory map.
|
|
|
|
The gem5 platform has been designed to implement a subset of the
|
|
original Versatile Express RS1 memory map. Off-chip peripherals should,
|
|
when possible, adhere to the Versatile Express memory map. Non-PCI
|
|
off-chip devices that are gem5-specific should live in the CS5 memory
|
|
space to avoid conflicts with existing devices that we might want to
|
|
model in the future. Such devices should normally have interrupts in
|
|
the gem5-specific SPI range.
|
|
|
|
On-chip peripherals are loosely modeled after the ARM CoreTile Express
|
|
A15x2 A7x3 memory and interrupt map. In particular, the GIC and
|
|
Generic Timer have the same interrupt lines and base addresses. Other
|
|
on-chip devices are gem5 specific.
|
|
|
|
Unlike the original Versatile Express RS2 extended platform, gem5 implements a
|
|
large contigious DRAM space, without aliases or holes, starting at the
|
|
2GiB boundary. This means that PCI memory is limited to 1GiB.
|
|
|
|
Memory map:
|
|
0x00000000-0x03ffffff: Boot memory (CS0)
|
|
0x04000000-0x07ffffff: Reserved
|
|
0x08000000-0x0bffffff: Reserved (CS0 alias)
|
|
0x0c000000-0x0fffffff: Reserved (Off-chip, CS4)
|
|
0x10000000-0x13ffffff: gem5-specific peripherals (Off-chip, CS5)
|
|
0x10000000-0x1000ffff: gem5 energy controller
|
|
0x10010000-0x1001ffff: gem5 pseudo-ops
|
|
|
|
0x14000000-0x17ffffff: Reserved (Off-chip, PSRAM, CS1)
|
|
0x18000000-0x1bffffff: Reserved (Off-chip, Peripherals, CS2)
|
|
0x1c000000-0x1fffffff: Peripheral block 1 (Off-chip, CS3):
|
|
0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
|
|
0x1c060000-0x1c06ffff: KMI0 (keyboard)
|
|
0x1c070000-0x1c07ffff: KMI1 (mouse)
|
|
0x1c090000-0x1c09ffff: UART0
|
|
0x1c0a0000-0x1c0affff: UART1 (reserved)
|
|
0x1c0b0000-0x1c0bffff: UART2 (reserved)
|
|
0x1c0c0000-0x1c0cffff: UART3 (reserved)
|
|
0x1c170000-0x1c17ffff: RTC
|
|
|
|
0x20000000-0x3fffffff: On-chip peripherals:
|
|
0x2b000000-0x2b00ffff: HDLCD
|
|
|
|
0x2c001000-0x2c001fff: GIC (distributor)
|
|
0x2c002000-0x2c0020ff: GIC (CPU interface)
|
|
0x2c004000-0x2c005fff: vGIC (HV)
|
|
0x2c006000-0x2c007fff: vGIC (VCPU)
|
|
0x2c1c0000-0x2c1cffff: GICv2m MSI frame 0
|
|
|
|
0x2d000000-0x2d00ffff: GPU (reserved)
|
|
|
|
0x2f000000-0x2fffffff: PCI IO space
|
|
0x30000000-0x3fffffff: PCI config space
|
|
|
|
0x40000000-0x7fffffff: Ext. AXI: Used as PCI memory
|
|
|
|
0x80000000-X: DRAM
|
|
|
|
Interrupts:
|
|
0- 15: Software generated interrupts (SGIs)
|
|
16- 31: On-chip private peripherals (PPIs)
|
|
25 : vgic
|
|
26 : generic_timer (hyp)
|
|
27 : generic_timer (virt)
|
|
28 : Reserved (Legacy FIQ)
|
|
29 : generic_timer (phys, sec)
|
|
30 : generic_timer (phys, non-sec)
|
|
31 : Reserved (Legacy IRQ)
|
|
32- 95: Mother board peripherals (SPIs)
|
|
32 : Reserved (SP805)
|
|
33 : Reserved (IOFPGA SW int)
|
|
34-35: Reserved (SP804)
|
|
36 : RTC
|
|
37-40: uart0-uart3
|
|
41-42: Reserved (PL180)
|
|
43 : Reserved (AACI)
|
|
44-45: kmi0-kmi1
|
|
46 : Reserved (CLCD)
|
|
47 : Reserved (Ethernet)
|
|
48 : Reserved (USB)
|
|
95-255: On-chip interrupt sources (we use these for
|
|
gem5-specific devices, SPIs)
|
|
95 : HDLCD
|
|
96- 98: GPU (reserved)
|
|
100-103: PCI
|
|
256-319: MSI frame 0 (gem5-specific, SPIs)
|
|
320-511: Unused
|
|
|
|
"""
|
|
|
|
# Everything above 2GiB is memory
|
|
_mem_regions = [(Addr('2GB'), Addr('510GB'))]
|
|
|
|
_off_chip_ranges = [
|
|
# CS1-CS5
|
|
AddrRange(0x0c000000, 0x1fffffff),
|
|
# External AXI interface (PCI)
|
|
AddrRange(0x2f000000, 0x7fffffff),
|
|
]
|
|
|
|
# Platform control device (off-chip)
|
|
realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000,
|
|
idreg=0x02250000, pio_addr=0x1c010000)
|
|
mcc = VExpressMCC()
|
|
dcc = CoreTile2A15DCC()
|
|
|
|
### On-chip devices ###
|
|
gic = kvm_gicv2_class(dist_addr=0x2c001000, cpu_addr=0x2c002000,
|
|
it_lines=512)
|
|
vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25)
|
|
gicv2m = Gicv2m()
|
|
gicv2m.frames = [
|
|
Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2c1c0000),
|
|
]
|
|
|
|
generic_timer = GenericTimer(int_phys=29, int_virt=27)
|
|
|
|
hdlcd = HDLcd(pxl_clk=dcc.osc_pxl,
|
|
pio_addr=0x2b000000, int_num=95)
|
|
|
|
def _on_chip_devices(self):
|
|
return [
|
|
self.gic, self.vgic, self.gicv2m,
|
|
self.hdlcd,
|
|
self.generic_timer,
|
|
]
|
|
|
|
### Off-chip devices ###
|
|
uart0 = Pl011(pio_addr=0x1c090000, int_num=37)
|
|
|
|
kmi0 = Pl050(pio_addr=0x1c060000, int_num=44)
|
|
kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True)
|
|
|
|
rtc = PL031(pio_addr=0x1c170000, int_num=36)
|
|
|
|
### gem5-specific off-chip devices ###
|
|
pci_host = GenericArmPciHost(
|
|
conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
|
|
pci_pio_base=0x2f000000,
|
|
int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
|
|
|
|
energy_ctrl = EnergyCtrl(pio_addr=0x10000000)
|
|
|
|
|
|
def _off_chip_devices(self):
|
|
return [
|
|
self.realview_io,
|
|
self.uart0,
|
|
self.kmi0, self.kmi1,
|
|
self.rtc,
|
|
self.pci_host,
|
|
self.energy_ctrl,
|
|
]
|
|
|
|
def attachPciDevice(self, device, *args, **kwargs):
|
|
device.host = self.pci_host
|
|
self._attach_device(device, *args, **kwargs)
|
|
|
|
def setupBootLoader(self, mem_bus, cur_sys, loc):
|
|
self.nvmem = SimpleMemory(range=AddrRange(0, size='64MB'),
|
|
conf_table_reported=False)
|
|
self.nvmem.port = mem_bus.master
|
|
if not cur_sys.boot_loader:
|
|
cur_sys.boot_loader = [ loc('boot_emm.arm64'), loc('boot_emm.arm') ]
|
|
cur_sys.atags_addr = 0x8000000
|
|
cur_sys.load_offset = 0x80000000
|
|
|
|
# Setup m5ops. It's technically not a part of the boot
|
|
# loader, but this is the only place we can configure the
|
|
# system.
|
|
cur_sys.m5ops_base = 0x10010000
|