Nilay Vaish 61434a9943 ruby: register multiple memory controllers ...

Currently the Ruby System maintains pointer to only one of the memory
controllers. But there can be multiple controllers in the system. This
patch adds a vector of memory controllers.

2012-10-15 17:27:17 -05:00

..

arch

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

base

Mem: Use range operations in bus in preparation for striping

2012-10-15 08:07:04 -04:00

cpu

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

dev

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

doc

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

doxygen

MEM: Put memory system document into doxygen

2012-09-25 11:49:41 -05:00

kern

SE: Ignore FUTEX_PRIVATE_FLAG of sys_futex

2012-09-21 04:51:18 -04:00

mem

ruby: register multiple memory controllers

2012-10-15 17:27:17 -05:00

python

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

sim

ruby: reset timing after cache warm up

2012-10-15 17:27:15 -05:00

unittest

AddrRange: Transition from Range<T> to AddrRange

2012-09-19 06:15:44 -04:00

Doxyfile

Doxygen: Update the version of the Doxyfile

2012-10-11 06:38:42 -04:00

SConscript

build: Add missing dependencies when building param SWIG interfaces

2012-09-25 11:49:40 -05:00