612f8f074f
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch. Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch. Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
687 lines
18 KiB
C++
687 lines
18 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2011-2013 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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SPAlignmentCheckCode = '''
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if (baseIsSP && bits(XBase, 3, 0) &&
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SPAlignmentCheckEnabled(xc->tcBase())) {
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return new SPAlignmentFault();
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}
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'''
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}};
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def template Load64Execute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template Store64Execute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA,
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memAccessFlags, NULL);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template Store64InitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
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NULL);
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}
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return fault;
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}
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}};
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def template StoreEx64Execute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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uint64_t writeResult = 0;
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if (fault == NoFault) {
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fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags,
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&writeResult);
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}
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if (fault == NoFault) {
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%(postacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreEx64InitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags,
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NULL);
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}
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return fault;
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}
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}};
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def template Load64InitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_src_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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fault = readMemTiming(xc, traceData, EA, Mem, memAccessFlags);
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}
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return fault;
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}
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}};
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def template Load64CompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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// ARM instructions will not have a pkt if the predicate is false
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getMem(pkt, Mem, traceData);
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template Store64CompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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return NoFault;
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}
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}};
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def template StoreEx64CompleteAcc {{
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Fault %(class_name)s::completeAcc(PacketPtr pkt,
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%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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uint64_t writeResult = pkt->req->getExtraData();
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%(postacc_code)s;
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template DCStore64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst, IntRegIndex _base, IntRegIndex _dest, uint64_t _imm);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template DCStore64Constructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _base, IntRegIndex _dest, uint64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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(IntRegIndex)_base, _dest, _imm)
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{
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%(constructor)s;
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assert(!%(use_uops)d);
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}
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}};
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def template DCStore64Execute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL);
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}
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if (fault == NoFault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template DCStore64InitiateAcc {{
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Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = NoFault;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == NoFault) {
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%(memacc_code)s;
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}
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if (fault == NoFault) {
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fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL);
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}
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return fault;
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}
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}};
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def template LoadStoreImm64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _base, int64_t _imm);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreImmU64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _base, int64_t _imm,
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bool noAlloc = false, bool exclusive = false,
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bool acrel = false);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreImmDU64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
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int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
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bool acrel = false);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template StoreImmDEx64Declare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, int64_t _imm = 0);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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};
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}};
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def template LoadStoreReg64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
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ArmExtendType _type, uint32_t _shiftAmt);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreRegU64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
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ArmExtendType _type, uint32_t _shiftAmt,
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bool noAlloc = false, bool exclusive = false,
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bool acrel = false);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreRaw64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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IntRegIndex _base);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreEx64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
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IntRegIndex _base, IntRegIndex _result);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreLit64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreLitU64Declare {{
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class %(class_name)s : public %(base_class)s
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{
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public:
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/// Constructor.
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%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm,
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bool noAlloc = false, bool exclusive = false,
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bool acrel = false);
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%(BasicExecDeclare)s
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%(InitiateAccDeclare)s
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%(CompleteAccDeclare)s
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virtual void
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annotateFault(ArmFault *fault) {
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%(fa_code)s
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}
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};
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}};
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def template LoadStoreImm64Constructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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(IntRegIndex)_dest, (IntRegIndex)_base, _imm)
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{
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%(constructor)s;
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#if %(use_uops)d
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assert(numMicroops >= 2);
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uops = new StaticInstPtr[numMicroops];
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uops[0] = new %(acc_name)s(machInst, _dest, _base, _imm);
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uops[0]->setDelayedCommit();
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uops[1] = new %(wb_decl)s;
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uops[1]->setLastMicroop();
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#endif
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}
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}};
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def template LoadStoreImmU64Constructor {{
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%(class_name)s::%(class_name)s(ExtMachInst machInst,
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IntRegIndex _dest, IntRegIndex _base, int64_t _imm,
|
|
bool noAlloc, bool exclusive, bool acrel)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _base, _imm)
|
|
{
|
|
%(constructor)s;
|
|
assert(!%(use_uops)d);
|
|
setExcAcRel(exclusive, acrel);
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreImmDU64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
|
|
int64_t _imm, bool noAlloc, bool exclusive, bool acrel)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _dest2, _base, _imm)
|
|
{
|
|
%(constructor)s;
|
|
assert(!%(use_uops)d);
|
|
setExcAcRel(exclusive, acrel);
|
|
}
|
|
}};
|
|
|
|
def template StoreImmDEx64Constructor {{
|
|
inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
|
|
IntRegIndex _base, int64_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_result, _dest, _dest2, _base, _imm)
|
|
{
|
|
%(constructor)s;
|
|
assert(!%(use_uops)d);
|
|
}
|
|
}};
|
|
|
|
|
|
def template LoadStoreReg64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
|
|
ArmExtendType _type, uint32_t _shiftAmt)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _base, _offset, _type, _shiftAmt)
|
|
{
|
|
%(constructor)s;
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _base, _offset,
|
|
_type, _shiftAmt);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreRegU64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
|
|
ArmExtendType _type, uint32_t _shiftAmt,
|
|
bool noAlloc, bool exclusive, bool acrel)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _base, _offset, _type, _shiftAmt)
|
|
{
|
|
%(constructor)s;
|
|
assert(!%(use_uops)d);
|
|
setExcAcRel(exclusive, acrel);
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreRaw64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, IntRegIndex _base)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base)
|
|
{
|
|
%(constructor)s;
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreEx64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
_dest, _base, _result)
|
|
{
|
|
%(constructor)s;
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreLit64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, int64_t _imm)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, _imm)
|
|
{
|
|
%(constructor)s;
|
|
#if %(use_uops)d
|
|
assert(numMicroops >= 2);
|
|
uops = new StaticInstPtr[numMicroops];
|
|
uops[0] = new %(acc_name)s(machInst, _dest, _imm);
|
|
uops[0]->setDelayedCommit();
|
|
uops[1] = new %(wb_decl)s;
|
|
uops[1]->setLastMicroop();
|
|
#endif
|
|
}
|
|
}};
|
|
|
|
def template LoadStoreLitU64Constructor {{
|
|
%(class_name)s::%(class_name)s(ExtMachInst machInst,
|
|
IntRegIndex _dest, int64_t _imm,
|
|
bool noAlloc, bool exclusive, bool acrel)
|
|
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
|
|
(IntRegIndex)_dest, _imm)
|
|
{
|
|
%(constructor)s;
|
|
assert(!%(use_uops)d);
|
|
setExcAcRel(exclusive, acrel);
|
|
}
|
|
}};
|