5de8ca9550
These changes enable a simple binary to be simulated in full system mode. Additionally, a new fault was implemented. It is executed once the CPU is initialized. This fault clears all interrupts and sets the pc to a reset vector. Change-Id: I50cfac91a61ba39a6ef3d38caca8794073887c88 Reviewed-on: https://gem5-review.googlesource.com/9061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
108 lines
3.2 KiB
C++
108 lines
3.2 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Jaidev Patwardhan
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* Robert Scheffel
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*/
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#ifndef __ARCH_RISCV_SYSTEM_HH__
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#define __ARCH_RISCV_SYSTEM_HH__
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#include <string>
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#include <vector>
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#include "base/loader/hex_file.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/pc_event.hh"
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#include "kern/system_events.hh"
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#include "params/RiscvSystem.hh"
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#include "sim/sim_object.hh"
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#include "sim/system.hh"
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class RiscvSystem : public System
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{
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protected:
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// checker for bare metal application
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bool _isBareMetal;
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// entry point for simulation
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Addr _resetVect;
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public:
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typedef RiscvSystemParams Params;
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RiscvSystem(Params *p);
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~RiscvSystem();
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// return reset vector
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Addr resetVect() const { return _resetVect; }
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// return bare metal checker
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bool isBareMetal() const { return _isBareMetal; }
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virtual bool breakpoint();
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public:
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/**
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* Set the m5RiscvAccess pointer in the console
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*/
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void setRiscvAccess(Addr access);
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/** console symbol table */
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SymbolTable *consoleSymtab;
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/** Object pointer for the console code */
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ObjectFile *console;
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/** Used by some Bare Iron Configurations */
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HexFile *hexFile;
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#ifndef NDEBUG
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/** Event to halt the simulator if the console calls panic() */
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BreakPCEvent *consolePanicEvent;
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#endif
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protected:
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const Params *params() const { return (const Params *)_params; }
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/** Add a function-based event to the console code. */
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template <class T>
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T *
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addConsoleFuncEvent(const char *lbl)
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{
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return addFuncEvent<T>(consoleSymtab, lbl);
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}
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virtual Addr fixFuncEventAddr(Addr addr);
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};
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#endif
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