d228a283c9
This change includes: 1) Verify available command bandwidth 2) Add support for multi-cycle commands 3) Add new timing parameters 4) Add ability to interleave bursts 5) Add LPDDR5 configurations The DRAM controller historically does not verify contention on the command bus and if there is adaquate command bandwidth to issue a new command. As memory technologies evolve, multiple cycles are becoming a requirement for some commands. Depending on the burst length, this can stress the command bandwidth. A check was added to verify command issue does not exceed a maximum value within a defined window. The default window is a burst, with the maximum value defined based on the burst length and media clocking characteristics. When the command bandwidth is exceeded, commands will be shifted to subsequent burst windows. Added support for multi-cycle commands, specifically Activate, which requires a larger address width as capacities grow. Additionally, added support for multi-cycle Read / Write bursts for low power DRAM cases in which additional CLK synchronization may be required to run at higher speeds. To support emerging memories, added the following new timing parameters. 1) tPPD -- Precharge-to-Precharge delay 2) tAAD -- Max delay between Activate-1 and Activate-2 commands I/O data rates are continuing to increase for DRAM but the core frequency is still fairly stagnant for many technologies. As we increase the burst length, either the core prefetch needs to increase (for a seamless burst) or the burst will be transferred with gaps on the data bus. To support the latter case, added the ability to interleave 2 bursts across bank groups. Using the changes above, added an initial set of LPDDR5 configurations. Change-Id: I1b14fed221350e6e403f7cbf089fe6c7f033c181 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26236 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com> Tested-by: kokoro <noreply+kokoro@google.com>
1513 lines
47 KiB
Python
1513 lines
47 KiB
Python
# Copyright (c) 2012-2020 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2013 Amin Farmahini-Farahani
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# Copyright (c) 2015 University of Kaiserslautern
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# Copyright (c) 2015 The University of Bologna
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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from m5.params import *
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from m5.proxy import *
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from m5.objects.AbstractMemory import *
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from m5.objects.QoSMemCtrl import *
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# Enum for memory scheduling algorithms, currently First-Come
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# First-Served and a First-Row Hit then First-Come First-Served
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class MemSched(Enum): vals = ['fcfs', 'frfcfs']
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# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting
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# channel, rank, bank, row and column, respectively, and going from
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# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are
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# suitable for an open-page policy, optimising for sequential accesses
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# hitting in the open row. For a closed-page policy, RoCoRaBaCh
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# maximises parallelism.
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class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh']
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# Enum for the page policy, either open, open_adaptive, close, or
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# close_adaptive.
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class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
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'close_adaptive']
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# DRAMCtrl is a single-channel single-ported DRAM controller model
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# that aims to model the most important system-level performance
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# effects of a DRAM without getting into too much detail of the DRAM
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# itself.
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class DRAMCtrl(QoSMemCtrl):
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type = 'DRAMCtrl'
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cxx_header = "mem/dram_ctrl.hh"
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# single-ported on the system interface side, instantiate with a
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# bus in front of the controller for multiple ports
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port = SlavePort("Slave port")
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# the basic configuration of the controller architecture, note
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# that each entry corresponds to a burst for the specific DRAM
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# configuration (e.g. x32 with burst length 8 is 32 bytes) and not
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# the cacheline size or request/packet size
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write_buffer_size = Param.Unsigned(64, "Number of write queue entries")
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read_buffer_size = Param.Unsigned(32, "Number of read queue entries")
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# threshold in percent for when to forcefully trigger writes and
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# start emptying the write buffer
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write_high_thresh_perc = Param.Percent(85, "Threshold to force writes")
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# threshold in percentage for when to start writes if the read
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# queue is empty
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write_low_thresh_perc = Param.Percent(50, "Threshold to start writes")
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# minimum write bursts to schedule before switching back to reads
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min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before "
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"switching to reads")
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# scheduler, address map and page policy
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mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy")
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addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy")
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page_policy = Param.PageManage('open_adaptive', "Page management policy")
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# enforce a limit on the number of accesses per row
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max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
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"closing");
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# size of DRAM Chip in Bytes
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device_size = Param.MemorySize("Size of DRAM chip")
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# pipeline latency of the controller and PHY, split into a
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# frontend part and a backend part, with reads and writes serviced
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# by the queues only seeing the frontend contribution, and reads
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# serviced by the memory seeing the sum of the two
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static_frontend_latency = Param.Latency("10ns", "Static frontend latency")
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static_backend_latency = Param.Latency("10ns", "Static backend latency")
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# the physical organisation of the DRAM
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device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\
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"device/chip")
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burst_length = Param.Unsigned("Burst lenght (BL) in beats")
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device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\
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"device/chip")
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devices_per_rank = Param.Unsigned("Number of devices/chips per rank")
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ranks_per_channel = Param.Unsigned("Number of ranks per channel")
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# default to 0 bank groups per rank, indicating bank group architecture
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# is not used
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# update per memory class when bank group architecture is supported
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bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank")
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banks_per_rank = Param.Unsigned("Number of banks per rank")
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# Enable DRAM powerdown states if True. This is False by default due to
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# performance being lower when enabled
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enable_dram_powerdown = Param.Bool(False, "Enable powerdown states")
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# For power modelling we need to know if the DRAM has a DLL or not
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dll = Param.Bool(True, "DRAM has DLL or not")
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# DRAMPower provides in addition to the core power, the possibility to
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# include RD/WR termination and IO power. This calculation assumes some
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# default values. The integration of DRAMPower with gem5 does not include
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# IO and RD/WR termination power by default. This might be added as an
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# additional feature in the future.
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# timing behaviour and constraints - all in nanoseconds
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# the base clock period of the DRAM
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tCK = Param.Latency("Clock period")
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# the amount of time in nanoseconds from issuing an activate command
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# to the data being available in the row buffer for a read/write
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tRCD = Param.Latency("RAS to CAS delay")
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# the time from issuing a read/write command to seeing the actual data
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tCL = Param.Latency("CAS latency")
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# minimum time between a precharge and subsequent activate
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tRP = Param.Latency("Row precharge time")
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# minimum time between an activate and a precharge to the same row
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tRAS = Param.Latency("ACT to PRE delay")
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# minimum time between a write data transfer and a precharge
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tWR = Param.Latency("Write recovery time")
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# minimum time between a read and precharge command
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tRTP = Param.Latency("Read to precharge")
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# time to complete a burst transfer, typically the burst length
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# divided by two due to the DDR bus, but by making it a parameter
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# it is easier to also evaluate SDR memories like WideIO.
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# This parameter has to account for burst length.
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# Read/Write requests with data size larger than one full burst are broken
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# down into multiple requests in the controller
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# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
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# With bank group architectures, tBURST represents the CAS-to-CAS
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# delay for bursts to different bank groups (tCCD_S)
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tBURST = Param.Latency("Burst duration "
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"(typically burst length / 2 cycles)")
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# tBURST_MAX is the column array cycle delay required before next access,
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# which could be greater than tBURST when the memory access time is greater
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# than tBURST
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tBURST_MAX = Param.Latency(Self.tBURST, "Column access delay")
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# tBURST_MIN is the minimum delay between bursts, which could be less than
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# tBURST when interleaving is supported
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tBURST_MIN = Param.Latency(Self.tBURST, "Minimim delay between bursts")
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# CAS-to-CAS delay for bursts to the same bank group
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# only utilized with bank group architectures; set to 0 for default case
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# tBURST is equivalent to tCCD_S; no explicit parameter required
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# for CAS-to-CAS delay for bursts to different bank groups
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tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
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# Write-to-Write delay for bursts to the same bank group
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# only utilized with bank group architectures; set to 0 for default case
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# This will be used to enable different same bank group delays
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# for writes versus reads
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tCCD_L_WR = Param.Latency(Self.tCCD_L,
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"Same bank group Write to Write delay")
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# time taken to complete one refresh cycle (N rows in all banks)
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tRFC = Param.Latency("Refresh cycle time")
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# refresh command interval, how often a "ref" command needs
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# to be sent. It is 7.8 us for a 64ms refresh requirement
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tREFI = Param.Latency("Refresh command interval")
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# write-to-read, same rank turnaround penalty
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tWTR = Param.Latency("Write to read, same rank switching time")
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# write-to-read, same rank turnaround penalty for same bank group
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tWTR_L = Param.Latency(Self.tWTR, "Write to read, same rank switching "
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"time, same bank group")
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# read-to-write, same rank turnaround penalty
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tRTW = Param.Latency("Read to write, same rank switching time")
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# rank-to-rank bus delay penalty
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# this does not correlate to a memory timing parameter and encompasses:
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# 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD
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# different rank bus delay
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tCS = Param.Latency("Rank to rank switching time")
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# minimum precharge to precharge delay time
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tPPD = Param.Latency("0ns", "PRE to PRE delay")
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# maximum delay between two-cycle ACT command phases
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tAAD = Param.Latency(Self.tCK,
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"Maximum delay between two-cycle ACT commands")
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two_cycle_activate = Param.Bool(False,
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"Two cycles required to send activate")
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# minimum row activate to row activate delay time
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tRRD = Param.Latency("ACT to ACT delay")
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# only utilized with bank group architectures; set to 0 for default case
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tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay")
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# time window in which a maximum number of activates are allowed
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# to take place, set to 0 to disable
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tXAW = Param.Latency("X activation window")
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activation_limit = Param.Unsigned("Max number of activates in window")
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# time to exit power-down mode
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# Exit power-down to next valid command delay
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tXP = Param.Latency("0ns", "Power-up Delay")
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# Exit Powerdown to commands requiring a locked DLL
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tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL")
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# time to exit self-refresh mode
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tXS = Param.Latency("0ns", "Self-refresh exit latency")
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# time to exit self-refresh mode with locked DLL
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tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL")
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# number of data beats per clock. with DDR, default is 2, one per edge
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beats_per_clock = Param.Unsigned(2, "Data beats per clock")
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data_clock_sync = Param.Bool(False, "Synchronization commands required")
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# Currently rolled into other params
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######################################################################
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# tRC - assumed to be tRAS + tRP
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# Power Behaviour and Constraints
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# DRAMs like LPDDR and WideIO have 2 external voltage domains. These are
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# defined as VDD and VDD2. Each current is defined for each voltage domain
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# separately. For example, current IDD0 is active-precharge current for
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# voltage domain VDD and current IDD02 is active-precharge current for
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# voltage domain VDD2.
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# By default all currents are set to 0mA. Users who are only interested in
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# the performance of DRAMs can leave them at 0.
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# Operating 1 Bank Active-Precharge current
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IDD0 = Param.Current("0mA", "Active precharge current")
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# Operating 1 Bank Active-Precharge current multiple voltage Range
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IDD02 = Param.Current("0mA", "Active precharge current VDD2")
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# Precharge Power-down Current: Slow exit
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IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow")
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# Precharge Power-down Current: Slow exit multiple voltage Range
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IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2")
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# Precharge Power-down Current: Fast exit
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IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast")
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# Precharge Power-down Current: Fast exit multiple voltage Range
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IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2")
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# Precharge Standby current
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IDD2N = Param.Current("0mA", "Precharge Standby current")
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# Precharge Standby current multiple voltage range
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IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2")
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# Active Power-down current: slow exit
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IDD3P0 = Param.Current("0mA", "Active Powerdown slow")
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# Active Power-down current: slow exit multiple voltage range
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IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2")
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# Active Power-down current : fast exit
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IDD3P1 = Param.Current("0mA", "Active Powerdown fast")
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# Active Power-down current : fast exit multiple voltage range
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IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2")
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# Active Standby current
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IDD3N = Param.Current("0mA", "Active Standby current")
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# Active Standby current multiple voltage range
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IDD3N2 = Param.Current("0mA", "Active Standby current VDD2")
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# Burst Read Operating Current
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IDD4R = Param.Current("0mA", "READ current")
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# Burst Read Operating Current multiple voltage range
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IDD4R2 = Param.Current("0mA", "READ current VDD2")
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# Burst Write Operating Current
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IDD4W = Param.Current("0mA", "WRITE current")
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# Burst Write Operating Current multiple voltage range
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IDD4W2 = Param.Current("0mA", "WRITE current VDD2")
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# Refresh Current
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IDD5 = Param.Current("0mA", "Refresh current")
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# Refresh Current multiple voltage range
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IDD52 = Param.Current("0mA", "Refresh current VDD2")
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# Self-Refresh Current
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IDD6 = Param.Current("0mA", "Self-refresh Current")
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# Self-Refresh Current multiple voltage range
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IDD62 = Param.Current("0mA", "Self-refresh Current VDD2")
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# Main voltage range of the DRAM
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VDD = Param.Voltage("0V", "Main Voltage Range")
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# Second voltage range defined by some DRAMs
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VDD2 = Param.Voltage("0V", "2nd Voltage Range")
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# A single DDR3-1600 x64 channel (one command and address bus), with
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# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
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# an 8x8 configuration.
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class DDR3_1600_8x8(DRAMCtrl):
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# size of device in bytes
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device_size = '512MB'
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# 8x8 configuration, 8 devices each with an 8-bit interface
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device_bus_width = 8
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# DDR3 is a BL8 device
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burst_length = 8
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# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
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device_rowbuffer_size = '1kB'
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# 8x8 configuration, so 8 devices
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devices_per_rank = 8
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# Use two ranks
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ranks_per_channel = 2
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# DDR3 has 8 banks in all configurations
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banks_per_rank = 8
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# 800 MHz
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tCK = '1.25ns'
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# 8 beats across an x64 interface translates to 4 clocks @ 800 MHz
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tBURST = '5ns'
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# DDR3-1600 11-11-11
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tRCD = '13.75ns'
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tCL = '13.75ns'
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tRP = '13.75ns'
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tRAS = '35ns'
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tRRD = '6ns'
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tXAW = '30ns'
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activation_limit = 4
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tRFC = '260ns'
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tWR = '15ns'
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# Greater of 4 CK or 7.5 ns
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tWTR = '7.5ns'
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# Greater of 4 CK or 7.5 ns
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tRTP = '7.5ns'
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# Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
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tRTW = '2.5ns'
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# Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
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tCS = '2.5ns'
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# <=85C, half for >85C
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tREFI = '7.8us'
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# active powerdown and precharge powerdown exit time
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tXP = '6ns'
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# self refresh exit time
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tXS = '270ns'
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# Current values from datasheet Die Rev E,J
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IDD0 = '55mA'
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IDD2N = '32mA'
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IDD3N = '38mA'
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IDD4W = '125mA'
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IDD4R = '157mA'
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IDD5 = '235mA'
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IDD3P1 = '38mA'
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IDD2P1 = '32mA'
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IDD6 = '20mA'
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VDD = '1.5V'
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# A single HMC-2500 x32 model based on:
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# [1] DRAMSpec: a high-level DRAM bank modelling tool
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# developed at the University of Kaiserslautern. This high level tool
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# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
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# estimate the DRAM bank latency and power numbers.
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# [2] High performance AXI-4.0 based interconnect for extensible smart memory
|
|
# cubes (E. Azarkhish et. al)
|
|
# Assumed for the HMC model is a 30 nm technology node.
|
|
# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
|
|
# layers).
|
|
# Each layer has 16 vaults and each vault consists of 2 banks per layer.
|
|
# In order to be able to use the same controller used for 2D DRAM generations
|
|
# for HMC, the following analogy is done:
|
|
# Channel (DDR) => Vault (HMC)
|
|
# device_size (DDR) => size of a single layer in a vault
|
|
# ranks per channel (DDR) => number of layers
|
|
# banks per rank (DDR) => banks per layer
|
|
# devices per rank (DDR) => devices per layer ( 1 for HMC).
|
|
# The parameters for which no input is available are inherited from the DDR3
|
|
# configuration.
|
|
# This configuration includes the latencies from the DRAM to the logic layer
|
|
# of the HMC
|
|
class HMC_2500_1x32(DDR3_1600_8x8):
|
|
# size of device
|
|
# two banks per device with each bank 4MB [2]
|
|
device_size = '8MB'
|
|
|
|
# 1x32 configuration, 1 device with 32 TSVs [2]
|
|
device_bus_width = 32
|
|
|
|
# HMC is a BL8 device [2]
|
|
burst_length = 8
|
|
|
|
# Each device has a page (row buffer) size of 256 bytes [2]
|
|
device_rowbuffer_size = '256B'
|
|
|
|
# 1x32 configuration, so 1 device [2]
|
|
devices_per_rank = 1
|
|
|
|
# 4 layers so 4 ranks [2]
|
|
ranks_per_channel = 4
|
|
|
|
# HMC has 2 banks per layer [2]
|
|
# Each layer represents a rank. With 4 layers and 8 banks in total, each
|
|
# layer has 2 banks; thus 2 banks per rank.
|
|
banks_per_rank = 2
|
|
|
|
# 1250 MHz [2]
|
|
tCK = '0.8ns'
|
|
|
|
# 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
|
|
tBURST = '3.2ns'
|
|
|
|
# Values using DRAMSpec HMC model [1]
|
|
tRCD = '10.2ns'
|
|
tCL = '9.9ns'
|
|
tRP = '7.7ns'
|
|
tRAS = '21.6ns'
|
|
|
|
# tRRD depends on the power supply network for each vendor.
|
|
# We assume a tRRD of a double bank approach to be equal to 4 clock
|
|
# cycles (Assumption)
|
|
tRRD = '3.2ns'
|
|
|
|
# activation limit is set to 0 since there are only 2 banks per vault
|
|
# layer.
|
|
activation_limit = 0
|
|
|
|
# Values using DRAMSpec HMC model [1]
|
|
tRFC = '59ns'
|
|
tWR = '8ns'
|
|
tRTP = '4.9ns'
|
|
|
|
# Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz =
|
|
# 0.8 ns (Assumption)
|
|
tCS = '0.8ns'
|
|
|
|
# Value using DRAMSpec HMC model [1]
|
|
tREFI = '3.9us'
|
|
|
|
# The default page policy in the vault controllers is simple closed page
|
|
# [2] nevertheless 'close' policy opens and closes the row multiple times
|
|
# for bursts largers than 32Bytes. For this reason we use 'close_adaptive'
|
|
page_policy = 'close_adaptive'
|
|
|
|
# RoCoRaBaCh resembles the default address mapping in HMC
|
|
addr_mapping = 'RoCoRaBaCh'
|
|
min_writes_per_switch = 8
|
|
|
|
# These parameters do not directly correlate with buffer_size in real
|
|
# hardware. Nevertheless, their value has been tuned to achieve a
|
|
# bandwidth similar to the cycle-accurate model in [2]
|
|
write_buffer_size = 32
|
|
read_buffer_size = 32
|
|
|
|
# The static latency of the vault controllers is estimated to be smaller
|
|
# than a full DRAM channel controller
|
|
static_backend_latency='4ns'
|
|
static_frontend_latency='4ns'
|
|
|
|
# A single DDR3-2133 x64 channel refining a selected subset of the
|
|
# options for the DDR-1600 configuration, based on the same DDR3-1600
|
|
# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
|
|
# consistent across the two configurations.
|
|
class DDR3_2133_8x8(DDR3_1600_8x8):
|
|
# 1066 MHz
|
|
tCK = '0.938ns'
|
|
|
|
# 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz
|
|
tBURST = '3.752ns'
|
|
|
|
# DDR3-2133 14-14-14
|
|
tRCD = '13.09ns'
|
|
tCL = '13.09ns'
|
|
tRP = '13.09ns'
|
|
tRAS = '33ns'
|
|
tRRD = '5ns'
|
|
tXAW = '25ns'
|
|
|
|
# Current values from datasheet
|
|
IDD0 = '70mA'
|
|
IDD2N = '37mA'
|
|
IDD3N = '44mA'
|
|
IDD4W = '157mA'
|
|
IDD4R = '191mA'
|
|
IDD5 = '250mA'
|
|
IDD3P1 = '44mA'
|
|
IDD2P1 = '43mA'
|
|
IDD6 ='20mA'
|
|
VDD = '1.5V'
|
|
|
|
# A single DDR4-2400 x64 channel (one command and address bus), with
|
|
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4)
|
|
# in an 16x4 configuration.
|
|
# Total channel capacity is 32GB
|
|
# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel
|
|
class DDR4_2400_16x4(DRAMCtrl):
|
|
# size of device
|
|
device_size = '1GB'
|
|
|
|
# 16x4 configuration, 16 devices each with a 4-bit interface
|
|
device_bus_width = 4
|
|
|
|
# DDR4 is a BL8 device
|
|
burst_length = 8
|
|
|
|
# Each device has a page (row buffer) size of 512 byte (1K columns x4)
|
|
device_rowbuffer_size = '512B'
|
|
|
|
# 16x4 configuration, so 16 devices
|
|
devices_per_rank = 16
|
|
|
|
# Match our DDR3 configurations which is dual rank
|
|
ranks_per_channel = 2
|
|
|
|
# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
|
|
# Set to 4 for x4 case
|
|
bank_groups_per_rank = 4
|
|
|
|
# DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
|
|
# configurations). Currently we do not capture the additional
|
|
# constraints incurred by the bank groups
|
|
banks_per_rank = 16
|
|
|
|
# override the default buffer sizes and go for something larger to
|
|
# accommodate the larger bank count
|
|
write_buffer_size = 128
|
|
read_buffer_size = 64
|
|
|
|
# 1200 MHz
|
|
tCK = '0.833ns'
|
|
|
|
# 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz
|
|
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
|
|
# With bank group architectures, tBURST represents the CAS-to-CAS
|
|
# delay for bursts to different bank groups (tCCD_S)
|
|
tBURST = '3.332ns'
|
|
|
|
# @2400 data rate, tCCD_L is 6 CK
|
|
# CAS-to-CAS delay for bursts to the same bank group
|
|
# tBURST is equivalent to tCCD_S; no explicit parameter required
|
|
# for CAS-to-CAS delay for bursts to different bank groups
|
|
tCCD_L = '5ns';
|
|
|
|
# DDR4-2400 17-17-17
|
|
tRCD = '14.16ns'
|
|
tCL = '14.16ns'
|
|
tRP = '14.16ns'
|
|
tRAS = '32ns'
|
|
|
|
# RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns)
|
|
tRRD = '3.332ns'
|
|
|
|
# RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns)
|
|
tRRD_L = '4.9ns';
|
|
|
|
# tFAW for 512B page is MAX(16 CK, 13ns)
|
|
tXAW = '13.328ns'
|
|
activation_limit = 4
|
|
# tRFC is 350ns
|
|
tRFC = '350ns'
|
|
|
|
tWR = '15ns'
|
|
|
|
# Here using the average of WTR_S and WTR_L
|
|
tWTR = '5ns'
|
|
|
|
# Greater of 4 CK or 7.5 ns
|
|
tRTP = '7.5ns'
|
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns
|
|
tRTW = '1.666ns'
|
|
|
|
# Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns
|
|
tCS = '1.666ns'
|
|
|
|
# <=85C, half for >85C
|
|
tREFI = '7.8us'
|
|
|
|
# active powerdown and precharge powerdown exit time
|
|
tXP = '6ns'
|
|
|
|
# self refresh exit time
|
|
# exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is:
|
|
# tRFC + 10ns = 340ns
|
|
tXS = '340ns'
|
|
|
|
# Current values from datasheet
|
|
IDD0 = '43mA'
|
|
IDD02 = '3mA'
|
|
IDD2N = '34mA'
|
|
IDD3N = '38mA'
|
|
IDD3N2 = '3mA'
|
|
IDD4W = '103mA'
|
|
IDD4R = '110mA'
|
|
IDD5 = '250mA'
|
|
IDD3P1 = '32mA'
|
|
IDD2P1 = '25mA'
|
|
IDD6 = '30mA'
|
|
VDD = '1.2V'
|
|
VDD2 = '2.5V'
|
|
|
|
# A single DDR4-2400 x64 channel (one command and address bus), with
|
|
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8)
|
|
# in an 8x8 configuration.
|
|
# Total channel capacity is 16GB
|
|
# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel
|
|
class DDR4_2400_8x8(DDR4_2400_16x4):
|
|
# 8x8 configuration, 8 devices each with an 8-bit interface
|
|
device_bus_width = 8
|
|
|
|
# Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
|
|
device_rowbuffer_size = '1kB'
|
|
|
|
# 8x8 configuration, so 8 devices
|
|
devices_per_rank = 8
|
|
|
|
# RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
|
|
tRRD_L = '4.9ns';
|
|
|
|
tXAW = '21ns'
|
|
|
|
# Current values from datasheet
|
|
IDD0 = '48mA'
|
|
IDD3N = '43mA'
|
|
IDD4W = '123mA'
|
|
IDD4R = '135mA'
|
|
IDD3P1 = '37mA'
|
|
|
|
# A single DDR4-2400 x64 channel (one command and address bus), with
|
|
# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16)
|
|
# in an 4x16 configuration.
|
|
# Total channel capacity is 4GB
|
|
# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel
|
|
class DDR4_2400_4x16(DDR4_2400_16x4):
|
|
# 4x16 configuration, 4 devices each with an 16-bit interface
|
|
device_bus_width = 16
|
|
|
|
# Each device has a page (row buffer) size of 2 Kbyte (1K columns x16)
|
|
device_rowbuffer_size = '2kB'
|
|
|
|
# 4x16 configuration, so 4 devices
|
|
devices_per_rank = 4
|
|
|
|
# Single rank for x16
|
|
ranks_per_channel = 1
|
|
|
|
# DDR4 has 2 (x16) or 4 (x4 and x8) bank groups
|
|
# Set to 2 for x16 case
|
|
bank_groups_per_rank = 2
|
|
|
|
# DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all
|
|
# configurations). Currently we do not capture the additional
|
|
# constraints incurred by the bank groups
|
|
banks_per_rank = 8
|
|
|
|
# RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns)
|
|
tRRD = '5.3ns'
|
|
|
|
# RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns)
|
|
tRRD_L = '6.4ns';
|
|
|
|
tXAW = '30ns'
|
|
|
|
# Current values from datasheet
|
|
IDD0 = '80mA'
|
|
IDD02 = '4mA'
|
|
IDD2N = '34mA'
|
|
IDD3N = '47mA'
|
|
IDD4W = '228mA'
|
|
IDD4R = '243mA'
|
|
IDD5 = '280mA'
|
|
IDD3P1 = '41mA'
|
|
|
|
# A single LPDDR2-S4 x32 interface (one command/address bus), with
|
|
# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1)
|
|
# in a 1x32 configuration.
|
|
class LPDDR2_S4_1066_1x32(DRAMCtrl):
|
|
# No DLL in LPDDR2
|
|
dll = False
|
|
|
|
# size of device
|
|
device_size = '512MB'
|
|
|
|
# 1x32 configuration, 1 device with a 32-bit interface
|
|
device_bus_width = 32
|
|
|
|
# LPDDR2_S4 is a BL4 and BL8 device
|
|
burst_length = 8
|
|
|
|
# Each device has a page (row buffer) size of 1KB
|
|
# (this depends on the memory density)
|
|
device_rowbuffer_size = '1kB'
|
|
|
|
# 1x32 configuration, so 1 device
|
|
devices_per_rank = 1
|
|
|
|
# Use a single rank
|
|
ranks_per_channel = 1
|
|
|
|
# LPDDR2-S4 has 8 banks in all configurations
|
|
banks_per_rank = 8
|
|
|
|
# 533 MHz
|
|
tCK = '1.876ns'
|
|
|
|
# Fixed at 15 ns
|
|
tRCD = '15ns'
|
|
|
|
# 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time
|
|
tCL = '15ns'
|
|
|
|
# Pre-charge one bank 15 ns (all banks 18 ns)
|
|
tRP = '15ns'
|
|
|
|
tRAS = '42ns'
|
|
tWR = '15ns'
|
|
|
|
tRTP = '7.5ns'
|
|
|
|
# 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz.
|
|
# Note this is a BL8 DDR device.
|
|
# Requests larger than 32 bytes are broken down into multiple requests
|
|
# in the controller
|
|
tBURST = '7.5ns'
|
|
|
|
# LPDDR2-S4, 4 Gbit
|
|
tRFC = '130ns'
|
|
tREFI = '3.9us'
|
|
|
|
# active powerdown and precharge powerdown exit time
|
|
tXP = '7.5ns'
|
|
|
|
# self refresh exit time
|
|
tXS = '140ns'
|
|
|
|
# Irrespective of speed grade, tWTR is 7.5 ns
|
|
tWTR = '7.5ns'
|
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns
|
|
tRTW = '3.75ns'
|
|
|
|
# Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns
|
|
tCS = '3.75ns'
|
|
|
|
# Activate to activate irrespective of density and speed grade
|
|
tRRD = '10.0ns'
|
|
|
|
# Irrespective of density, tFAW is 50 ns
|
|
tXAW = '50ns'
|
|
activation_limit = 4
|
|
|
|
# Current values from datasheet
|
|
IDD0 = '15mA'
|
|
IDD02 = '70mA'
|
|
IDD2N = '2mA'
|
|
IDD2N2 = '30mA'
|
|
IDD3N = '2.5mA'
|
|
IDD3N2 = '30mA'
|
|
IDD4W = '10mA'
|
|
IDD4W2 = '190mA'
|
|
IDD4R = '3mA'
|
|
IDD4R2 = '220mA'
|
|
IDD5 = '40mA'
|
|
IDD52 = '150mA'
|
|
IDD3P1 = '1.2mA'
|
|
IDD3P12 = '8mA'
|
|
IDD2P1 = '0.6mA'
|
|
IDD2P12 = '0.8mA'
|
|
IDD6 = '1mA'
|
|
IDD62 = '3.2mA'
|
|
VDD = '1.8V'
|
|
VDD2 = '1.2V'
|
|
|
|
# A single WideIO x128 interface (one command and address bus), with
|
|
# default timings based on an estimated WIO-200 8 Gbit part.
|
|
class WideIO_200_1x128(DRAMCtrl):
|
|
# No DLL for WideIO
|
|
dll = False
|
|
|
|
# size of device
|
|
device_size = '1024MB'
|
|
|
|
# 1x128 configuration, 1 device with a 128-bit interface
|
|
device_bus_width = 128
|
|
|
|
# This is a BL4 device
|
|
burst_length = 4
|
|
|
|
# Each device has a page (row buffer) size of 4KB
|
|
# (this depends on the memory density)
|
|
device_rowbuffer_size = '4kB'
|
|
|
|
# 1x128 configuration, so 1 device
|
|
devices_per_rank = 1
|
|
|
|
# Use one rank for a one-high die stack
|
|
ranks_per_channel = 1
|
|
|
|
# WideIO has 4 banks in all configurations
|
|
banks_per_rank = 4
|
|
|
|
# 200 MHz
|
|
tCK = '5ns'
|
|
|
|
# WIO-200
|
|
tRCD = '18ns'
|
|
tCL = '18ns'
|
|
tRP = '18ns'
|
|
tRAS = '42ns'
|
|
tWR = '15ns'
|
|
# Read to precharge is same as the burst
|
|
tRTP = '20ns'
|
|
|
|
# 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz.
|
|
# Note this is a BL4 SDR device.
|
|
tBURST = '20ns'
|
|
|
|
# WIO 8 Gb
|
|
tRFC = '210ns'
|
|
|
|
# WIO 8 Gb, <=85C, half for >85C
|
|
tREFI = '3.9us'
|
|
|
|
# Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns
|
|
tWTR = '15ns'
|
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns
|
|
tRTW = '10ns'
|
|
|
|
# Default different rank bus delay to 2 CK, @200 MHz = 10 ns
|
|
tCS = '10ns'
|
|
|
|
# Activate to activate irrespective of density and speed grade
|
|
tRRD = '10.0ns'
|
|
|
|
# Two instead of four activation window
|
|
tXAW = '50ns'
|
|
activation_limit = 2
|
|
|
|
# The WideIO specification does not provide current information
|
|
|
|
# A single LPDDR3 x32 interface (one command/address bus), with
|
|
# default timings based on a LPDDR3-1600 4 Gbit part (Micron
|
|
# EDF8132A1MC) in a 1x32 configuration.
|
|
class LPDDR3_1600_1x32(DRAMCtrl):
|
|
# No DLL for LPDDR3
|
|
dll = False
|
|
|
|
# size of device
|
|
device_size = '512MB'
|
|
|
|
# 1x32 configuration, 1 device with a 32-bit interface
|
|
device_bus_width = 32
|
|
|
|
# LPDDR3 is a BL8 device
|
|
burst_length = 8
|
|
|
|
# Each device has a page (row buffer) size of 4KB
|
|
device_rowbuffer_size = '4kB'
|
|
|
|
# 1x32 configuration, so 1 device
|
|
devices_per_rank = 1
|
|
|
|
# Technically the datasheet is a dual-rank package, but for
|
|
# comparison with the LPDDR2 config we stick to a single rank
|
|
ranks_per_channel = 1
|
|
|
|
# LPDDR3 has 8 banks in all configurations
|
|
banks_per_rank = 8
|
|
|
|
# 800 MHz
|
|
tCK = '1.25ns'
|
|
|
|
tRCD = '18ns'
|
|
|
|
# 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time
|
|
tCL = '15ns'
|
|
|
|
tRAS = '42ns'
|
|
tWR = '15ns'
|
|
|
|
# Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns
|
|
tRTP = '7.5ns'
|
|
|
|
# Pre-charge one bank 18 ns (all banks 21 ns)
|
|
tRP = '18ns'
|
|
|
|
# 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz.
|
|
# Note this is a BL8 DDR device.
|
|
# Requests larger than 32 bytes are broken down into multiple requests
|
|
# in the controller
|
|
tBURST = '5ns'
|
|
|
|
# LPDDR3, 4 Gb
|
|
tRFC = '130ns'
|
|
tREFI = '3.9us'
|
|
|
|
# active powerdown and precharge powerdown exit time
|
|
tXP = '7.5ns'
|
|
|
|
# self refresh exit time
|
|
tXS = '140ns'
|
|
|
|
# Irrespective of speed grade, tWTR is 7.5 ns
|
|
tWTR = '7.5ns'
|
|
|
|
# Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns
|
|
tRTW = '2.5ns'
|
|
|
|
# Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns
|
|
tCS = '2.5ns'
|
|
|
|
# Activate to activate irrespective of density and speed grade
|
|
tRRD = '10.0ns'
|
|
|
|
# Irrespective of size, tFAW is 50 ns
|
|
tXAW = '50ns'
|
|
activation_limit = 4
|
|
|
|
# Current values from datasheet
|
|
IDD0 = '8mA'
|
|
IDD02 = '60mA'
|
|
IDD2N = '0.8mA'
|
|
IDD2N2 = '26mA'
|
|
IDD3N = '2mA'
|
|
IDD3N2 = '34mA'
|
|
IDD4W = '2mA'
|
|
IDD4W2 = '190mA'
|
|
IDD4R = '2mA'
|
|
IDD4R2 = '230mA'
|
|
IDD5 = '28mA'
|
|
IDD52 = '150mA'
|
|
IDD3P1 = '1.4mA'
|
|
IDD3P12 = '11mA'
|
|
IDD2P1 = '0.8mA'
|
|
IDD2P12 = '1.8mA'
|
|
IDD6 = '0.5mA'
|
|
IDD62 = '1.8mA'
|
|
VDD = '1.8V'
|
|
VDD2 = '1.2V'
|
|
|
|
# A single GDDR5 x64 interface, with
|
|
# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix
|
|
# H5GQ1H24AFR) in a 2x32 configuration.
|
|
class GDDR5_4000_2x32(DRAMCtrl):
|
|
# size of device
|
|
device_size = '128MB'
|
|
|
|
# 2x32 configuration, 1 device with a 32-bit interface
|
|
device_bus_width = 32
|
|
|
|
# GDDR5 is a BL8 device
|
|
burst_length = 8
|
|
|
|
# Each device has a page (row buffer) size of 2Kbits (256Bytes)
|
|
device_rowbuffer_size = '256B'
|
|
|
|
# 2x32 configuration, so 2 devices
|
|
devices_per_rank = 2
|
|
|
|
# assume single rank
|
|
ranks_per_channel = 1
|
|
|
|
# GDDR5 has 4 bank groups
|
|
bank_groups_per_rank = 4
|
|
|
|
# GDDR5 has 16 banks with 4 bank groups
|
|
banks_per_rank = 16
|
|
|
|
# 1000 MHz
|
|
tCK = '1ns'
|
|
|
|
# 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz
|
|
# Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz )
|
|
# 8 beats at 4000 MHz = 2 beats at 1000 MHz
|
|
# tBURST is equivalent to the CAS-to-CAS delay (tCCD)
|
|
# With bank group architectures, tBURST represents the CAS-to-CAS
|
|
# delay for bursts to different bank groups (tCCD_S)
|
|
tBURST = '2ns'
|
|
|
|
# @1000MHz data rate, tCCD_L is 3 CK
|
|
# CAS-to-CAS delay for bursts to the same bank group
|
|
# tBURST is equivalent to tCCD_S; no explicit parameter required
|
|
# for CAS-to-CAS delay for bursts to different bank groups
|
|
tCCD_L = '3ns';
|
|
|
|
tRCD = '12ns'
|
|
|
|
# tCL is not directly found in datasheet and assumed equal tRCD
|
|
tCL = '12ns'
|
|
|
|
tRP = '12ns'
|
|
tRAS = '28ns'
|
|
|
|
# RRD_S (different bank group)
|
|
# RRD_S is 5.5 ns in datasheet.
|
|
# rounded to the next multiple of tCK
|
|
tRRD = '6ns'
|
|
|
|
# RRD_L (same bank group)
|
|
# RRD_L is 5.5 ns in datasheet.
|
|
# rounded to the next multiple of tCK
|
|
tRRD_L = '6ns'
|
|
|
|
tXAW = '23ns'
|
|
|
|
# tXAW < 4 x tRRD.
|
|
# Therefore, activation limit is set to 0
|
|
activation_limit = 0
|
|
|
|
tRFC = '65ns'
|
|
tWR = '12ns'
|
|
|
|
# Here using the average of WTR_S and WTR_L
|
|
tWTR = '5ns'
|
|
|
|
# Read-to-Precharge 2 CK
|
|
tRTP = '2ns'
|
|
|
|
# Assume 2 cycles
|
|
tRTW = '2ns'
|
|
|
|
# A single HBM x128 interface (one command and address bus), with
|
|
# default timings based on data publically released
|
|
# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
|
|
# IDD measurement values, and by extrapolating data from other classes.
|
|
# Architecture values based on published HBM spec
|
|
# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
|
|
class HBM_1000_4H_1x128(DRAMCtrl):
|
|
# HBM gen1 supports up to 8 128-bit physical channels
|
|
# Configuration defines a single channel, with the capacity
|
|
# set to (full_ stack_capacity / 8) based on 2Gb dies
|
|
# To use all 8 channels, set 'channels' parameter to 8 in
|
|
# system configuration
|
|
|
|
# 128-bit interface legacy mode
|
|
device_bus_width = 128
|
|
|
|
# HBM supports BL4 and BL2 (legacy mode only)
|
|
burst_length = 4
|
|
|
|
# size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
|
|
# with 8 channels, 128MB per channel
|
|
device_size = '128MB'
|
|
|
|
device_rowbuffer_size = '2kB'
|
|
|
|
# 1x128 configuration
|
|
devices_per_rank = 1
|
|
|
|
# HBM does not have a CS pin; set rank to 1
|
|
ranks_per_channel = 1
|
|
|
|
# HBM has 8 or 16 banks depending on capacity
|
|
# 2Gb dies have 8 banks
|
|
banks_per_rank = 8
|
|
|
|
# depending on frequency, bank groups may be required
|
|
# will always have 4 bank groups when enabled
|
|
# current specifications do not define the minimum frequency for
|
|
# bank group architecture
|
|
# setting bank_groups_per_rank to 0 to disable until range is defined
|
|
bank_groups_per_rank = 0
|
|
|
|
# 500 MHz for 1Gbps DDR data rate
|
|
tCK = '2ns'
|
|
|
|
# use values from IDD measurement in JEDEC spec
|
|
# use tRP value for tRCD and tCL similar to other classes
|
|
tRP = '15ns'
|
|
tRCD = '15ns'
|
|
tCL = '15ns'
|
|
tRAS = '33ns'
|
|
|
|
# BL2 and BL4 supported, default to BL4
|
|
# DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
|
|
tBURST = '4ns'
|
|
|
|
# value for 2Gb device from JEDEC spec
|
|
tRFC = '160ns'
|
|
|
|
# value for 2Gb device from JEDEC spec
|
|
tREFI = '3.9us'
|
|
|
|
# extrapolate the following from LPDDR configs, using ns values
|
|
# to minimize burst length, prefetch differences
|
|
tWR = '18ns'
|
|
tRTP = '7.5ns'
|
|
tWTR = '10ns'
|
|
|
|
# start with 2 cycles turnaround, similar to other memory classes
|
|
# could be more with variations across the stack
|
|
tRTW = '4ns'
|
|
|
|
# single rank device, set to 0
|
|
tCS = '0ns'
|
|
|
|
# from MemCon example, tRRD is 4ns with 2ns tCK
|
|
tRRD = '4ns'
|
|
|
|
# from MemCon example, tFAW is 30ns with 2ns tCK
|
|
tXAW = '30ns'
|
|
activation_limit = 4
|
|
|
|
# 4tCK
|
|
tXP = '8ns'
|
|
|
|
# start with tRFC + tXP -> 160ns + 8ns = 168ns
|
|
tXS = '168ns'
|
|
|
|
# A single HBM x64 interface (one command and address bus), with
|
|
# default timings based on HBM gen1 and data publically released
|
|
# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
|
|
# Note: This defines a pseudo-channel with a unique controller
|
|
# instantiated per pseudo-channel
|
|
# Stay at same IO rate (1Gbps) to maintain timing relationship with
|
|
# HBM gen1 class (HBM_1000_4H_x128) where possible
|
|
class HBM_1000_4H_1x64(HBM_1000_4H_1x128):
|
|
# For HBM gen2 with pseudo-channel mode, configure 2X channels.
|
|
# Configuration defines a single pseudo channel, with the capacity
|
|
# set to (full_ stack_capacity / 16) based on 8Gb dies
|
|
# To use all 16 pseudo channels, set 'channels' parameter to 16 in
|
|
# system configuration
|
|
|
|
# 64-bit pseudo-channle interface
|
|
device_bus_width = 64
|
|
|
|
# HBM pseudo-channel only supports BL4
|
|
burst_length = 4
|
|
|
|
# size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
|
|
# with 16 channels, 256MB per channel
|
|
device_size = '256MB'
|
|
|
|
# page size is halved with pseudo-channel; maintaining the same same number
|
|
# of rows per pseudo-channel with 2X banks across 2 channels
|
|
device_rowbuffer_size = '1kB'
|
|
|
|
# HBM has 8 or 16 banks depending on capacity
|
|
# Starting with 4Gb dies, 16 banks are defined
|
|
banks_per_rank = 16
|
|
|
|
# reset tRFC for larger, 8Gb device
|
|
# use HBM1 4Gb value as a starting point
|
|
tRFC = '260ns'
|
|
|
|
# start with tRFC + tXP -> 160ns + 8ns = 168ns
|
|
tXS = '268ns'
|
|
# Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
|
|
tCS = '2ns'
|
|
tREFI = '3.9us'
|
|
|
|
# active powerdown and precharge powerdown exit time
|
|
tXP = '10ns'
|
|
|
|
# self refresh exit time
|
|
tXS = '65ns'
|
|
|
|
# A single LPDDR5 x16 interface (one command/address bus)
|
|
# for a single x16 channel with default timings based on
|
|
# initial JEDEC specification
|
|
# Starting with 5.5Gbps data rates and 8Gbit die
|
|
# Configuring for 16-bank mode with bank-group architecture
|
|
# burst of 32, which means bursts can be interleaved
|
|
class LPDDR5_5500_1x16_BG_BL32(DRAMCtrl):
|
|
|
|
# Increase buffer size to account for more bank resources
|
|
read_buffer_size = 64
|
|
|
|
# Set page policy to better suit DMC Huxley
|
|
page_policy = 'close_adaptive'
|
|
|
|
# 16-bit channel interface
|
|
device_bus_width = 16
|
|
|
|
# LPDDR5 is a BL16 or BL32 device
|
|
# With BG mode, BL16 and BL32 are supported
|
|
# Use BL32 for higher command bandwidth
|
|
burst_length = 32
|
|
|
|
# size of device in bytes
|
|
device_size = '1GB'
|
|
|
|
# 2kB page with BG mode
|
|
device_rowbuffer_size = '2kB'
|
|
|
|
# Use a 1x16 configuration
|
|
devices_per_rank = 1
|
|
|
|
# Use a single rank
|
|
ranks_per_channel = 1
|
|
|
|
# LPDDR5 supports configurable bank options
|
|
# 8B : BL32, all frequencies
|
|
# 16B : BL32 or BL16, <=3.2Gbps
|
|
# 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
|
|
# Initial configuration will have 16 banks with Bank Group Arch
|
|
# to maximim resources and enable higher data rates
|
|
banks_per_rank = 16
|
|
bank_groups_per_rank = 4
|
|
|
|
# 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
|
|
tCK = '1.455ns'
|
|
|
|
# Greater of 2 CK or 18ns
|
|
tRCD = '18ns'
|
|
|
|
# Base RL is 16 CK @ 687.5 MHz = 23.28ns
|
|
tCL = '23.280ns'
|
|
|
|
# Greater of 2 CK or 18ns
|
|
tRP = '18ns'
|
|
|
|
# Greater of 3 CK or 42ns
|
|
tRAS = '42ns'
|
|
|
|
# Greater of 3 CK or 34ns
|
|
tWR = '34ns'
|
|
|
|
# active powerdown and precharge powerdown exit time
|
|
# Greater of 3 CK or 7ns
|
|
tXP = '7ns'
|
|
|
|
# self refresh exit time (tRFCab + 7.5ns)
|
|
tXS = '217.5ns'
|
|
|
|
# Greater of 2 CK or 7.5 ns minus 2 CK
|
|
tRTP = '4.59ns'
|
|
|
|
# With BG architecture, burst of 32 transferred in two 16-beat
|
|
# sub-bursts, with a 16-beat gap in between.
|
|
# Each 16-beat sub-burst is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
|
|
# tBURST is the delay to transfer the Bstof32 = 6 CK @ 687.5 MHz
|
|
tBURST = '8.73ns'
|
|
# can interleave a Bstof32 from another bank group at tBURST_MIN
|
|
# 16-beats is 8 WCK @2.75 GHz or 2 CK @ 687.5 MHz
|
|
tBURST_MIN = '2.91ns'
|
|
# tBURST_MAX is the maximum burst delay for same bank group timing
|
|
# this is 8 CK @ 687.5 MHz
|
|
tBURST_MAX = '11.64ns'
|
|
|
|
# 8 CK @ 687.5 MHz
|
|
tCCD_L = "11.64ns"
|
|
|
|
# LPDDR5, 8 Gbit/channel for 280ns tRFCab
|
|
tRFC = '210ns'
|
|
tREFI = '3.9us'
|
|
|
|
# Greater of 4 CK or 6.25 ns
|
|
tWTR = '6.25ns'
|
|
# Greater of 4 CK or 12 ns
|
|
tWTR_L = '12ns'
|
|
|
|
# Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
|
|
# tWCKDQ0/tCK will be 1 CK for most cases
|
|
# For gem5 RL = WL and BL/n is already accounted for with tBURST
|
|
# Result is and additional 1 CK is required
|
|
tRTW = '1.455ns'
|
|
|
|
# Default different rank bus delay to 2 CK, @687.5 MHz = 2.91 ns
|
|
tCS = '2.91ns'
|
|
|
|
# 2 CK
|
|
tPPD = '2.91ns'
|
|
|
|
# Greater of 2 CK or 5 ns
|
|
tRRD = '5ns'
|
|
tRRD_L = '5ns'
|
|
|
|
# With Bank Group Arch mode tFAW is 20 ns
|
|
tXAW = '20ns'
|
|
activation_limit = 4
|
|
|
|
# at 5Gbps, 4:1 WCK to CK ratio required
|
|
# 2 data beats per WCK (DDR) -> 8 per CK
|
|
beats_per_clock = 8
|
|
|
|
# 2 cycles required to send activate command
|
|
# 2 command phases can be sent back-to-back or
|
|
# with a gap up to tAAD = 8 CK
|
|
two_cycle_activate = True
|
|
tAAD = '11.640ns'
|
|
|
|
data_clock_sync = True
|
|
|
|
# A single LPDDR5 x16 interface (one command/address bus)
|
|
# for a single x16 channel with default timings based on
|
|
# initial JEDEC specification
|
|
# Starting with 5.5Gbps data rates and 8Gbit die
|
|
# Configuring for 16-bank mode with bank-group architecture, burst of 16
|
|
class LPDDR5_5500_1x16_BG_BL16(LPDDR5_5500_1x16_BG_BL32):
|
|
|
|
# LPDDR5 is a BL16 or BL32 device
|
|
# With BG mode, BL16 and BL32 are supported
|
|
# Use BL16 for smaller access granularity
|
|
burst_length = 16
|
|
|
|
# For Bstof16 with BG arch, 2 CK @ 687.5 MHz with 4:1 clock ratio
|
|
tBURST = '2.91ns'
|
|
tBURST_MIN = '2.91ns'
|
|
# For Bstof16 with BG arch, 4 CK @ 687.5 MHz with 4:1 clock ratio
|
|
tBURST_MAX = '5.82ns'
|
|
|
|
# 4 CK @ 687.5 MHz
|
|
tCCD_L = "5.82ns"
|
|
|
|
|
|
# A single LPDDR5 x16 interface (one command/address bus)
|
|
# for a single x16 channel with default timings based on
|
|
# initial JEDEC specification
|
|
# Starting with 5.5Gbps data rates and 8Gbit die
|
|
# Configuring for 8-bank mode, burst of 32
|
|
class LPDDR5_5500_1x16_8B_BL32(LPDDR5_5500_1x16_BG_BL32):
|
|
|
|
# 4kB page with 8B mode
|
|
device_rowbuffer_size = '4kB'
|
|
|
|
# LPDDR5 supports configurable bank options
|
|
# 8B : BL32, all frequencies
|
|
# 16B : BL32 or BL16, <=3.2Gbps
|
|
# 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
|
|
# Select 8B
|
|
banks_per_rank = 8
|
|
bank_groups_per_rank = 0
|
|
|
|
# For Bstof32 with 8B mode, 4 CK @ 687.5 MHz with 4:1 clock ratio
|
|
tBURST = '5.82ns'
|
|
tBURST_MIN = '5.82ns'
|
|
tBURST_MAX = '5.82ns'
|
|
|
|
# Greater of 4 CK or 12 ns
|
|
tWTR = '12ns'
|
|
|
|
# Greater of 2 CK or 10 ns
|
|
tRRD = '10ns'
|
|
|
|
# With 8B mode tFAW is 40 ns
|
|
tXAW = '40ns'
|
|
activation_limit = 4
|
|
|
|
# Reset BG arch timing for 8B mode
|
|
tCCD_L = "0ns"
|
|
tRRD_L = "0ns"
|
|
tWTR_L = "0ns"
|
|
|
|
# A single LPDDR5 x16 interface (one command/address bus)
|
|
# for a single x16 channel with default timings based on
|
|
# initial JEDEC specification
|
|
# 6.4Gbps data rates and 8Gbit die
|
|
# Configuring for 16-bank mode with bank-group architecture
|
|
# burst of 32, which means bursts can be interleaved
|
|
class LPDDR5_6400_1x16_BG_BL32(LPDDR5_5500_1x16_BG_BL32):
|
|
|
|
# 5.5Gb/s DDR with 4:1 WCK:CK ratio for 687.5 MHz CK
|
|
tCK = '1.25ns'
|
|
|
|
# Base RL is 17 CK @ 800 MHz = 21.25ns
|
|
tCL = '21.25ns'
|
|
|
|
# With BG architecture, burst of 32 transferred in two 16-beat
|
|
# sub-bursts, with a 16-beat gap in between.
|
|
# Each 16-beat sub-burst is 8 WCK @3.2 GHz or 2 CK @ 800 MHz
|
|
# tBURST is the delay to transfer the Bstof32 = 6 CK @ 800 MHz
|
|
tBURST = '7.5ns'
|
|
# can interleave a Bstof32 from another bank group at tBURST_MIN
|
|
# 16-beats is 8 WCK @2.3 GHz or 2 CK @ 800 MHz
|
|
tBURST_MIN = '2.5ns'
|
|
# tBURST_MAX is the maximum burst delay for same bank group timing
|
|
# this is 8 CK @ 800 MHz
|
|
tBURST_MAX = '10ns'
|
|
|
|
# 8 CK @ 800 MHz
|
|
tCCD_L = "10ns"
|
|
|
|
# Required RD-to-WR timing is RL+ BL/n + tWCKDQ0/tCK - WL
|
|
# tWCKDQ0/tCK will be 1 CK for most cases
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# For gem5 RL = WL and BL/n is already accounted for with tBURST
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# Result is and additional 1 CK is required
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tRTW = '1.25ns'
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# Default different rank bus delay to 2 CK, @687.5 MHz = 2.5 ns
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tCS = '2.5ns'
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# 2 CK
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tPPD = '2.5ns'
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# 2 command phases can be sent back-to-back or
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# with a gap up to tAAD = 8 CK
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tAAD = '10ns'
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# A single LPDDR5 x16 interface (one command/address bus)
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# for a single x16 channel with default timings based on initial
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# JEDEC specifcation
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# 6.4Gbps data rates and 8Gbit die
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# Configuring for 16-bank mode with bank-group architecture, burst of 16
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class LPDDR5_6400_1x16_BG_BL16(LPDDR5_6400_1x16_BG_BL32):
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# LPDDR5 is a BL16 or BL32 device
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# With BG mode, BL16 and BL32 are supported
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# Use BL16 for smaller access granularity
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burst_length = 16
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# For Bstof16 with BG arch, 2 CK @ 800 MHz with 4:1 clock ratio
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tBURST = '2.5ns'
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tBURST_MIN = '2.5ns'
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# For Bstof16 with BG arch, 4 CK @ 800 MHz with 4:1 clock ratio
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tBURST_MAX = '5ns'
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# 4 CK @ 800 MHz
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tCCD_L = "5ns"
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# A single LPDDR5 x16 interface (one command/address bus)
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# for a single x16 channel with default timings based on
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# initial JEDEC specification
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# 6.4Gbps data rates and 8Gbit die
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# Configuring for 8-bank mode, burst of 32
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class LPDDR5_6400_1x16_8B_BL32(LPDDR5_6400_1x16_BG_BL32):
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# 4kB page with 8B mode
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device_rowbuffer_size = '4kB'
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# LPDDR5 supports configurable bank options
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# 8B : BL32, all frequencies
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# 16B : BL32 or BL16, <=3.2Gbps
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# 16B with Bank Group Arch (4B/BG): BL32 or BL16, >3.2Gbps
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# Select 8B
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banks_per_rank = 8
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bank_groups_per_rank = 0
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# For Bstof32 with 8B mode, 4 CK @ 800 MHz with 4:1 clock ratio
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tBURST = '5ns'
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tBURST_MIN = '5ns'
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tBURST_MAX = '5ns'
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# Greater of 4 CK or 12 ns
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tWTR = '12ns'
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# Greater of 2 CK or 10 ns
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tRRD = '10ns'
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# With 8B mode tFAW is 40 ns
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tXAW = '40ns'
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activation_limit = 4
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# Reset BG arch timing for 8B mode
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tCCD_L = "0ns"
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tRRD_L = "0ns"
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tWTR_L = "0ns"
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