Files
gem5/src/cpu/simple_thread.cc
Timothy Hayes 5c83d8f74c cpu: Allow storing an invalid HTM checkpoint
Commits 02745afd and f9b4e32 introduced a mechanism for creating checkpoint
objects for hardware transactional memory (HTM) and Arm TME. Because the
checkpoint object also contains the local UID of a transaction, it is
needed before any architectural checkpointing takes places. This caused
segfaults when running HTM codes.

This commit allows ISAs to allocate a checkpoint once at the beginning
of simulation.  In order to do that we need to remove the validity check
assertion; the cpt will become valid only after a first successfull
transaction start

Change-Id: I233d01805f8ab655131ed8cd6404950a2bf6fbc7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
2020-09-29 09:16:28 +00:00

201 lines
5.9 KiB
C++

/*
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#include "cpu/simple_thread.hh"
#include <string>
#include "arch/utility.hh"
#include "base/callback.hh"
#include "base/compiler.hh"
#include "base/cprintf.hh"
#include "base/output.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "cpu/base.hh"
#include "cpu/simple/base.hh"
#include "cpu/thread_context.hh"
#include "mem/se_translating_port_proxy.hh"
#include "mem/translating_port_proxy.hh"
#include "params/BaseCPU.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
using namespace std;
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
Process *_process, BaseTLB *_itb,
BaseTLB *_dtb, BaseISA *_isa)
: ThreadState(_cpu, _thread_num, _process),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
system(_sys), itb(_itb), dtb(_dtb), decoder(isa),
htmTransactionStarts(0), htmTransactionStops(0)
{
assert(isa);
clearArchRegs();
}
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
BaseTLB *_itb, BaseTLB *_dtb, BaseISA *_isa)
: ThreadState(_cpu, _thread_num, NULL),
isa(dynamic_cast<TheISA::ISA *>(_isa)),
predicate(true), memAccPredicate(true),
comInstEventQueue("instruction-based event queue"),
system(_sys), itb(_itb), dtb(_dtb), decoder(isa),
htmTransactionStarts(0), htmTransactionStops(0)
{
assert(isa);
clearArchRegs();
}
void
SimpleThread::takeOverFrom(ThreadContext *oldContext)
{
::takeOverFrom(*this, *oldContext);
decoder.takeOverFrom(oldContext->getDecoderPtr());
isa->takeOverFrom(this, oldContext);
funcExeInst = oldContext->readFuncExeInst();
storeCondFailures = 0;
}
void
SimpleThread::copyState(ThreadContext *oldContext)
{
// copy over functional state
_status = oldContext->status();
copyArchRegs(oldContext);
if (FullSystem)
funcExeInst = oldContext->readFuncExeInst();
_threadId = oldContext->threadId();
_contextId = oldContext->contextId();
}
void
SimpleThread::serialize(CheckpointOut &cp) const
{
ThreadState::serialize(cp);
::serialize(*this, cp);
}
void
SimpleThread::unserialize(CheckpointIn &cp)
{
ThreadState::unserialize(cp);
::unserialize(*this, cp);
}
void
SimpleThread::activate()
{
if (status() == ThreadContext::Active)
return;
lastActivate = curTick();
_status = ThreadContext::Active;
baseCpu->activateContext(_threadId);
}
void
SimpleThread::suspend()
{
if (status() == ThreadContext::Suspended)
return;
lastActivate = curTick();
lastSuspend = curTick();
_status = ThreadContext::Suspended;
baseCpu->suspendContext(_threadId);
}
void
SimpleThread::halt()
{
if (status() == ThreadContext::Halted)
return;
_status = ThreadContext::Halted;
baseCpu->haltContext(_threadId);
}
void
SimpleThread::copyArchRegs(ThreadContext *src_tc)
{
TheISA::copyRegs(src_tc, this);
}
// hardware transactional memory
void
SimpleThread::htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)
{
BaseSimpleCPU *baseSimpleCpu = dynamic_cast<BaseSimpleCPU*>(baseCpu);
assert(baseSimpleCpu);
baseSimpleCpu->htmSendAbortSignal(cause);
// these must be reset after the abort signal has been sent
htmTransactionStarts = 0;
htmTransactionStops = 0;
}
BaseHTMCheckpointPtr&
SimpleThread::getHtmCheckpointPtr()
{
return _htmCheckpoint;
}
void
SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
{
_htmCheckpoint = std::move(new_cpt);
}