Commits02745afdandf9b4e32introduced a mechanism for creating checkpoint objects for hardware transactional memory (HTM) and Arm TME. Because the checkpoint object also contains the local UID of a transaction, it is needed before any architectural checkpointing takes places. This caused segfaults when running HTM codes. This commit allows ISAs to allocate a checkpoint once at the beginning of simulation. In order to do that we need to remove the validity check assertion; the cpt will become valid only after a first successfull transaction start Change-Id: I233d01805f8ab655131ed8cd6404950a2bf6fbc7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35015 Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
201 lines
5.9 KiB
C++
201 lines
5.9 KiB
C++
/*
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* Copyright (c) 2018, 2020 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/simple_thread.hh"
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#include <string>
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#include "arch/utility.hh"
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#include "base/callback.hh"
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#include "base/compiler.hh"
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#include "base/cprintf.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/base.hh"
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#include "cpu/simple/base.hh"
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#include "cpu/thread_context.hh"
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#include "mem/se_translating_port_proxy.hh"
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#include "mem/translating_port_proxy.hh"
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#include "params/BaseCPU.hh"
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#include "sim/faults.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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#include "sim/serialize.hh"
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#include "sim/sim_exit.hh"
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#include "sim/system.hh"
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using namespace std;
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// constructor
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SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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Process *_process, BaseTLB *_itb,
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BaseTLB *_dtb, BaseISA *_isa)
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: ThreadState(_cpu, _thread_num, _process),
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isa(dynamic_cast<TheISA::ISA *>(_isa)),
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predicate(true), memAccPredicate(true),
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comInstEventQueue("instruction-based event queue"),
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system(_sys), itb(_itb), dtb(_dtb), decoder(isa),
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htmTransactionStarts(0), htmTransactionStops(0)
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{
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assert(isa);
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clearArchRegs();
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}
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SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
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BaseTLB *_itb, BaseTLB *_dtb, BaseISA *_isa)
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: ThreadState(_cpu, _thread_num, NULL),
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isa(dynamic_cast<TheISA::ISA *>(_isa)),
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predicate(true), memAccPredicate(true),
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comInstEventQueue("instruction-based event queue"),
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system(_sys), itb(_itb), dtb(_dtb), decoder(isa),
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htmTransactionStarts(0), htmTransactionStops(0)
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{
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assert(isa);
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clearArchRegs();
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}
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void
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SimpleThread::takeOverFrom(ThreadContext *oldContext)
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{
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::takeOverFrom(*this, *oldContext);
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decoder.takeOverFrom(oldContext->getDecoderPtr());
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isa->takeOverFrom(this, oldContext);
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funcExeInst = oldContext->readFuncExeInst();
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storeCondFailures = 0;
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}
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void
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SimpleThread::copyState(ThreadContext *oldContext)
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{
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// copy over functional state
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_status = oldContext->status();
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copyArchRegs(oldContext);
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if (FullSystem)
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funcExeInst = oldContext->readFuncExeInst();
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_threadId = oldContext->threadId();
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_contextId = oldContext->contextId();
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}
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void
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SimpleThread::serialize(CheckpointOut &cp) const
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{
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ThreadState::serialize(cp);
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::serialize(*this, cp);
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}
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void
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SimpleThread::unserialize(CheckpointIn &cp)
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{
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ThreadState::unserialize(cp);
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::unserialize(*this, cp);
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}
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void
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SimpleThread::activate()
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{
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if (status() == ThreadContext::Active)
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return;
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lastActivate = curTick();
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_status = ThreadContext::Active;
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baseCpu->activateContext(_threadId);
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}
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void
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SimpleThread::suspend()
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{
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if (status() == ThreadContext::Suspended)
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return;
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lastActivate = curTick();
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lastSuspend = curTick();
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_status = ThreadContext::Suspended;
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baseCpu->suspendContext(_threadId);
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}
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void
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SimpleThread::halt()
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{
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if (status() == ThreadContext::Halted)
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return;
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_status = ThreadContext::Halted;
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baseCpu->haltContext(_threadId);
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}
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void
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SimpleThread::copyArchRegs(ThreadContext *src_tc)
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{
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TheISA::copyRegs(src_tc, this);
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}
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// hardware transactional memory
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void
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SimpleThread::htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause)
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{
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BaseSimpleCPU *baseSimpleCpu = dynamic_cast<BaseSimpleCPU*>(baseCpu);
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assert(baseSimpleCpu);
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baseSimpleCpu->htmSendAbortSignal(cause);
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// these must be reset after the abort signal has been sent
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htmTransactionStarts = 0;
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htmTransactionStops = 0;
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}
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BaseHTMCheckpointPtr&
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SimpleThread::getHtmCheckpointPtr()
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{
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return _htmCheckpoint;
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}
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void
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SimpleThread::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
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{
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_htmCheckpoint = std::move(new_cpt);
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}
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