5c7192daed
src/SConscript:
strip doesn't take a src and dest in solaris
--HG--
extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
98 lines
3.8 KiB
Python
98 lines
3.8 KiB
Python
from m5.params import *
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from m5.proxy import *
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from Device import BasicPioDevice, IsaFake, BadAddr
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from Uart import Uart8250
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from Platform import Platform
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from SimConsole import SimConsole, ConsoleListener
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class MmDisk(BasicPioDevice):
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type = 'MmDisk'
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image = Param.DiskImage("Disk Image")
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pio_addr = 0x1F40000000
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class DumbTOD(BasicPioDevice):
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type = 'DumbTOD'
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time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
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pio_addr = 0xfff0c1fff8
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class T1000(Platform):
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type = 'T1000'
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system = Param.System(Parent.any, "system")
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fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
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#warn_access="Accessing Clock Unit -- Unimplemented!")
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fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
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ret_data64=0x0000000000000000, update_data=False)
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#warn_access="Accessing Memory Banks -- Unimplemented!")
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fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000)
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#warn_access="Accessing IOB -- Unimplemented!")
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fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
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#warn_access="Accessing JBI -- Unimplemented!")
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fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
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ret_data64=0x0000000000000001, update_data=True)
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#warn_access="Accessing L2 Cache Banks -- Unimplemented!")
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fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
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ret_data64=0x0000000000000000, update_data=True)
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#warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
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fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
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#warn_access="Accessing SSI -- Unimplemented!")
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hvuart = Uart8250(pio_addr=0xfff0c2c000)
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htod = DumbTOD()
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puart0 = Uart8250(pio_addr=0x1f10000000)
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console = SimConsole(listener = ConsoleListener())
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.fake_clk.pio = bus.port
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self.fake_membnks.pio = bus.port
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self.fake_iob.pio = bus.port
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self.fake_jbi.pio = bus.port
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self.fake_l2_1.pio = bus.port
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self.fake_l2_2.pio = bus.port
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self.fake_l2_3.pio = bus.port
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self.fake_l2_4.pio = bus.port
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self.fake_l2esr_1.pio = bus.port
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self.fake_l2esr_2.pio = bus.port
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self.fake_l2esr_3.pio = bus.port
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self.fake_l2esr_4.pio = bus.port
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self.fake_ssi.pio = bus.port
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self.puart0.pio = bus.port
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self.hvuart.pio = bus.port
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self.htod.pio = bus.port
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