Logo
Explore Help
Sign In
derek/gem5
1
0
Fork 0
You've already forked gem5
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
5c6835ae3fb398fe8aa83ac8b4c806dd6e800b44
gem5/arch
History
Gabe Black 5c6835ae3f Fixed a couple typos
--HG--
extra : convert_revision : 2ffbfc4755e46a119c9709d6a5e9ddc41fde45e0
2006-03-17 14:25:54 -05:00
..
alpha
Merge m5.eecs.umich.edu:/bk/newmem
2006-03-16 14:08:31 -05:00
mips
fix to LiveProcess (this change got deleted somehow)
2006-03-16 19:01:09 -05:00
sparc
Fixed a couple typos
2006-03-17 14:25:54 -05:00
isa_parser.py
Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
2006-03-14 15:55:00 -05:00
isa_specific.hh
Minor Sconscript edit ... mips decoder changes ... initialize NNPC and output fault name in simple cpu
2006-03-14 18:28:51 -05:00
SConscript
Moved registerfile.hh to regfile.hh
2006-03-14 16:05:44 -05:00
Powered by Gitea Version: 1.25.4 Page: 29ms Template: 10ms
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API