Andreas Hansson 5c2c3f598e mem: Make DRAM read/write switching less conservative ...

This patch changes the read/write event loop to use a single event
(nextReqEvent), along with a state variable, thus joining the two
control flows. This change makes it easier to follow the state
transitions, and control what happens when.

With the new loop we modify the overly conservative switching times
such that the write-to-read switch allows bank preparation to happen
in parallel with the bus turn around. Similarly, the read-to-write
switch uses the introduced tRTW constraint.

2014-05-09 18:58:48 -04:00

..

cache

mem: Squash prefetch requests from downstream caches

2014-05-09 18:58:46 -04:00

protocol

ruby: slicc: change enqueue statement

2014-04-08 13:26:30 -05:00

ruby

ruby: recorder: Fix (de-)serializing with different cache block-sizes

2014-04-19 09:00:30 -05:00

slicc

ruby: slicc: remove old documentation

2014-04-19 09:00:31 -05:00

abstract_mem.cc

mem: Wakeup sleeping CPUs without caches on LLSC

2014-03-07 15:56:23 -05:00

abstract_mem.hh

mem: Avoid explicitly zeroing the memory backing store

2013-05-30 12:53:54 -04:00

AbstractMemory.py

mem: Change AbstractMemory defaults to match the common case

2013-08-19 03:52:33 -04:00

addr_mapper.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

addr_mapper.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

AddrMapper.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

bridge.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

bridge.hh

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

Bridge.py

mem: Tidy up the bridge with const and additional checks

2013-06-27 05:49:49 -04:00

bus.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

Bus.py

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

coherent_bus.cc

mem: Make returning snoop responses occupy response layer

2013-05-30 12:54:02 -04:00

coherent_bus.hh

mem: De-virtualise interfaces in the CoherentBus

2013-10-17 10:20:45 -05:00

comm_monitor.cc

mem: Auto-generate CommMonitor trace file names

2014-05-09 18:58:46 -04:00

comm_monitor.hh

mem: CommMonitor trace warn on non-timing mode

2014-03-23 11:11:40 -04:00

CommMonitor.py

mem: Auto-generate CommMonitor trace file names

2014-05-09 18:58:46 -04:00

dram_ctrl.cc

mem: Make DRAM read/write switching less conservative

2014-05-09 18:58:48 -04:00

dram_ctrl.hh

mem: Make DRAM read/write switching less conservative

2014-05-09 18:58:48 -04:00

DRAMCtrl.py

mem: Make DRAM read/write switching less conservative

2014-05-09 18:58:48 -04:00

dramsim2_wrapper.cc

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

dramsim2_wrapper.hh

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

dramsim2.cc

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

dramsim2.hh

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

DRAMSim2.py

mem: Add a wrapped DRAMSim2 memory controller

2014-02-18 05:50:53 -05:00

fs_translating_port_proxy.cc

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

fs_translating_port_proxy.hh

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

mem_object.cc

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

mem_object.hh

Port: Add protocol-agnostic ports in the port hierarchy

2012-10-15 08:12:35 -04:00

MemObject.py

sim: Include object header files in SWIG interfaces

2012-11-02 11:32:01 -05:00

mport.cc

MEM: Separate snoops and normal memory requests/responses

2012-04-14 05:45:07 -04:00

mport.hh

MEM: Separate requests and responses for timing accesses

2012-05-01 13:40:42 -04:00

noncoherent_bus.cc

mem: Make the buses multi layered

2013-05-30 12:54:01 -04:00

noncoherent_bus.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

packet_access.hh

arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh

2009-09-23 08:34:21 -07:00

packet_queue.cc

mem: Adding verbose debug output in the memory system

2013-04-22 13:20:33 -04:00

packet_queue.hh

sim: have a curTick per eventq

2012-11-16 10:27:47 -06:00

packet.cc

mem: Add support for a security bit in the memory system

2014-01-24 15:29:30 -06:00

packet.hh

mem: Squash prefetch requests from downstream caches

2014-05-09 18:58:46 -04:00

page_table.cc

sim: Fix two bugs relating to software caching of PageTable entries.

2013-04-23 09:47:52 -04:00

page_table.hh

sim: Fix two bugs relating to software caching of PageTable entries.

2013-04-23 09:47:52 -04:00

physical.cc

mem: Fix bug in PhysicalMemory use of mmap and munmap

2014-02-18 05:51:01 -05:00

physical.hh

mem: Merge ranges that are part of the conf table

2013-01-07 13:05:38 -05:00

port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port_proxy.hh

arch: Resurrect the NOISA build target and rename it NULL

2013-09-04 13:22:57 -04:00

port.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

port.hh

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

qport.hh

ruby: Simplify RubyPort flow control and routing

2014-02-23 19:16:16 -06:00

request.hh

mem: prefetcher: add options, support for unaligned addresses

2014-01-29 23:21:25 -06:00

SConscript

mem: Rename SimpleDRAM to a more suitable DRAMCtrl

2014-03-23 11:12:12 -04:00

se_translating_port_proxy.cc

mem: Set the cache line size on a system level

2013-07-18 08:31:16 -04:00

se_translating_port_proxy.hh

MEM: Introduce the master/slave port sub-classes in C++

2012-03-30 09:40:11 -04:00

simple_mem.cc

mem: Fix scheduling bug in SimpleMemory

2013-09-18 08:46:33 -04:00

simple_mem.hh

mem: Add an internal packet queue in SimpleMemory

2013-08-19 03:52:25 -04:00

SimpleMemory.py

mem: Add an internal packet queue in SimpleMemory

2013-08-19 03:52:25 -04:00

tport.cc

mem: Replace check with panic where inhibited should not happen

2013-04-22 13:20:33 -04:00

tport.hh

Port: Hide the queue implementation in SimpleTimingPort

2012-07-09 12:35:42 -04:00